• Microelectronics
  • Vol. 53, Issue 3, 396 (2023)
YANG Yonghui, ZHANG Jinlong, ZHANG Guangsheng, HUANG Dong, and ZHU Kunfeng
Author Affiliations
  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.220298 Cite this Article
    YANG Yonghui, ZHANG Jinlong, ZHANG Guangsheng, HUANG Dong, ZHU Kunfeng. A Rail-to-Rail I/O Operational Amplifier[J]. Microelectronics, 2023, 53(3): 396 Copy Citation Text show less

    Abstract

    A rail to rail operational amplifier was designed based on CMOS technology. The whole circuit includes bias circuit, input stage, output stage and ESD protection circuit. A new architecture was used in the input stage of the circuit. Rail to rail input could be realized through a pair of depletion NMOS tubes as input tubes. At the same time, the common source common grid structure was adopted in the input stage, which could provide high common mode input range and gain. In the output stage, class AB output stage is used to obtain full swing output. At the same time, the ESD protection circuit adopts the traditional ggmos circuit, and the withstand voltage is greater than 2 kV. After simulation, it can be seen that the input bias current of the circuit is 150 fA. When the load is 100 kΩ, the maximum and minimum output voltage can reach the range of 20 mV from the power rail and ground rail. When the power voltage is 5 V, 80 dB CMRR and 120 dB gain can be obtained, the phase margin is about 50 °, and the unit gain bandwidth is about 15 MHz.
    YANG Yonghui, ZHANG Jinlong, ZHANG Guangsheng, HUANG Dong, ZHU Kunfeng. A Rail-to-Rail I/O Operational Amplifier[J]. Microelectronics, 2023, 53(3): 396
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