[1] AN B, HUANG S, CHEN Z, et al. A 16 bit 1 MS/s high-bit sampling SAR ADC with improved binaryweighted capacitive array [C] // 2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM). Nanjing, China. 2020.
[4] GUO W, ZHUANG H, SUN N. A 13 b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators [C] // 2017 Symposium on VLSI Circuits.Kyoto, Japan. 2017.
[5] ZHUANG H Y, GUO W J, LIU J X, et al. A second-order noise-shaping SAR ADC with passive integrator and tri-level voting [J]. IEEE Journal of Solid-State Circuits, 2019, 54(6): 1636-1647.
[6] LIU J X, WANG X, GAO Z J, et al. A 40 kHz-BW 90 dB-SNDR noise-shaping SAR with 4×passive gain and 2nd-order mismatch error shaping [C] // IEEE ISSCC. San Francisco, CA, USA. 2020: 158-159.
[7] HU J, LI D Q, ZHU Z M, et al. A 10-kS/s 625-Hzbandwidth 65-dB SNDR 2nd-order noise-shaping_SAR ADC for biomedical sensor applications [J]. IEEE Sensors Journal, 2020, 20(23): 13881-13891.
[8] ZHOU J D, DUAN J H. A 8 kHz-bandwidth 13.7 bit-ENOB low-power noise-shaping SAR ADC using split-capacitor DAC [C] // 2021 6th International Conference on Integrated Circuits and Microsystems(ICICM). Nanjing, China. 2021.
[9] TANG X Y, YANG X X, ZHAO W D, et al. A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVTrobust closed-loop dynamic amplififier [J]. IEEE Journal of Solid-State Circuits, 2020, 55(12): 3248-3259.