Aiming at first-order noise shaping (NS), which often compromises power consumption to achieve a high effective number of bits (ENOB) and oversampling rate (OSR), this study proposes a second-order passive NS SAR ADC with a low OSR and low power consumption, whose higher passive gain can better suppress the noise of the comparator, and the residual voltage is achieved by multiplexing the integrating capacitors through the switching MOS array. Thus, the generation of the residual sampling capacitance clearing and residual sampling kT/C noise is avoided, reducing the total kT/C noise. Based on a 180 nm CMOS process, the simulation results show that without digital calibration, the designed 10-bit second-order passive NS SAR ADC circuit achieves an ENOB of 13.5 bits at a sampling rate of 100 kS/s with an OSR of 5. The power consumption is 6.98 μW.