This research presented a digital decimation filter with ultra-low power and small area in the audio signal Σ-Δ analog-to-digital converters. The filter consisted of the cascaded integrating comb filter, the low order compensator, and the all-pass polyphase IIR filter. Compared with the conventional FIR filter, it contained lower orders and hardware complexity. Meanwhile, it could achieve high decimation, ultra-low passband ripple, high stopband attenuation and approximately linear phase. The overall effective bandwidth was 20 kHz, and the decimation factor was 128. The ASIC design was implemented in a 0.18 μm CMOS process. The digital layout area was 0.37 mm2, and the power was 125 μW. The SNR reached 98.79 dB, and the effective accuracy achieved 16 bit. Compared with that of the decimation filter of traditional FIR structure, the area of the proposed digital decimation filter was reduced by 60% and the power consumption was cut down by 20%.