[1] ALI A M A, DINC H, BHORASKAR P, et al. A 14 b 2.5 GS/s and 5 GS/s RF sampling ADC with background calibration and dither [C]// VLSI-Circuits. Honolulu, HI, USA. 2016: 206-207.
[2] ALI A M A, DINC H , BHORASKAR P , et al. A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration [J]. IEEE J Sol Sta Circ, 2014, 49(12): 2857-2867.
[3] SETTERBERG B, POULTON K, RAY S, et al. A 14 b 2.5 GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction [C]// ISSCC Dig Pap. San Francisco, CA, USA. 2013: 466-468.
[4] RAZZAGHI A, TAM S W, KALKHORAN P, et al. A single-channel 10 b 1 GS/s ADC with 1-cycle latency using pipelined cascaded folding [C]// IEEE Bipolar/BiCMOS Circ Tech Meet. Monterey, CA, USA. 2008: 265-268.
[5] CHANTIER N, NICOLAS S, MORISSON R, et al. 12 bit 1.5 GS/s L-band ADC on 200 GHz SiGeC technology [C]// IEEE CIE Int Conf Radar. Chengdu, China. 2012: 265-268.
[9] DINC H, ALLEN P E. A 1.2 GSample/s double-switching CMOS THA with -62 dB THD [J]. IEEE J Sol Sta Circ, 2009, 44(3): 848-861.
[10] BOCK J, SCHAFER H, AUFINGER K, et al. SiGe bipolar technology for automotive radar applications [C]// Bipolar/BiCMOS Circ Tech Meet. Montreal, Canada. 2004: 84-87.
[12] ZIMMER T, BCK J, BUCHALI F, et al. SiGe HBTs and BiCMOS technology for present and future millimeter-wave systems [J]. IEEE J Microwave, 2021, 1(1): 288-298.