• Microelectronics
  • Vol. 52, Issue 4, 597 (2022)
XU Mingyuan1, FU Dongbing2, ZHU Can1, ZHANG Lei1, WANG Yan1, and LI Liang3
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.210431 Cite this Article
    XU Mingyuan, FU Dongbing, ZHU Can, ZHANG Lei, WANG Yan, LI Liang. A Low Latency Folding and Interpolation 12 bit 1.5 GS/s ADC[J]. Microelectronics, 2022, 52(4): 597 Copy Citation Text show less

    Abstract

    Based on a 4-stage cascade folding interpolation architecture, a 12-bit ADC was presented. The circuit was designed in a 0.18 μm SiGe BiCMOS process. The single core achieved a conversion speed of 1.5 GS/s, the output interface was 2-lane LVDS, and the latency was less than 7 ns. The front-end sample/hold circuit and folding interpolation quantizer adopted pure bipolar design, which could achieve 12 bit quantization accuracy without trimming. Finally, the design points and test results of the published layout were given.
    XU Mingyuan, FU Dongbing, ZHU Can, ZHANG Lei, WANG Yan, LI Liang. A Low Latency Folding and Interpolation 12 bit 1.5 GS/s ADC[J]. Microelectronics, 2022, 52(4): 597
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