Wireless implanted integrated circuits (IC) are becoming attractive in biomedical applications recently^{[1, 2]}. The wireless power and data transfer telemetry (WPDT) sub-system is essential for the implanted ICs to transfer power and control data from the external transmitter, as shown in Fig. 1. Binary-phase-shift keying (BPSK) is particularly well-suited for the downlink data communication of wireless power and data transfer (WPDT) systems due to its high conversion efficiency, compatibility with narrowband inductive links, and robust immunity to amplitude noise. While amplitude-shift keying (ASK) and frequency-shift keying (FSK) are commonly employed modulation schemes, each with distinct data encoding methods through modulation of amplitude, frequency, they exhibit specific limitations. ASK, for instance, though straightforward and easily demodulated, is highly sensitive to variations in coil distance and external magnetic interference. ON−OFF keying (OOK) enhances ASK’s immunity by achieving a high modulation index (e.g., 100%)^[3]. However, this improvement comes at the expense of power transmission efficiency due to carrier discontinuities during ON intervals. FSK modulations^[4], while resilient to background interference, impose significant spectrum demands that constrain data rates, particularly in medical implantable devices where low-frequency carriers. Hence, designing a BPSK demodulator with small area, ultra-low power and sufficient data rate is significant^[5].

Recently, several BPSK demodulators have been reported, which can be categorized into the PLL-based^[6−8] and PLL-less approaches^[9−11]. The PLL-based approach has been demonstrated to be suitable for the inductive link with high-Q coils^[6]. Yet, it is power hungry mainly due to the static power of voltage-controlled oscillator (VCO) and charge pump (CP) in the PLL; and the loop bandwidth is limited for the stability consideration, thus requiring a large integral capacitor C_INT^[12] with slow data rate. In contrast, using the edge-detection method without oscillator, CP and large capacitor, the PLL-less BPSK demodulator achieves much higher data rate with lower power and smaller area. However, it is not suitable for the use of high-Q coils because the phase of the received BPSK signal on the secondary coil needs a few cycles to invert its phase when data transition occurs, thus neutralizing the edge-detection scheme^{[6, 7]}.

In this paper, we propose a PLL-based BPSK demodulator, which not only supports high-Q coils but also achieves comparable high data rate and compact size compared to prior PLL-less approaches. The loop-filter-less (LPF-less) PLL is proposed to make the PLL output phase track the input phase in real time by cutting the LPF, hence significantly increasing the data rate and reducing area concurrently. Meanwhile, the energy efficiency is also obviously improved thanks to the free of the static power in our LPF-less PLL.

Fig. 2 depicts the block diagram of the proposed PLL-based BPSK demodulator. It consists of our devised LPF-less PLL, a timing starter (TS), an edge alignment calibrator (EAC), a trigger detector (TD) and a clock and data recovery block (CDR). Thanks to the removal of the LPF, the PLL output PLL_OUT can track the phase of its input BPSK_IN in real time. So, the data rate is improved with significantly shrunk area. Meanwhile, power reduction is realized due to the free from the PLL static power, as detailed in Section 2.1. The EAC along with the TS aligns the rising edge of PLL_OUT and BPSK_IN, and generates two edge-aligned signals: PLL_DL and BPSK_SYN. Since there is a delay between the PLL_DL and BPSK_SYN, a phase difference step between the two signals is generated when input data transition occurs. Thus, TD can detect such phase difference to generate a trigger signal TR for the CDR to recover the modulated data D_OUT with its synchronized clock CK_OUT. DR_MAX is used to select if the demodulator operates at its maximum data rate (f_carrier/2) or not, and the ratio between data rate and f_carrier is controlled by DRSEL. The details of the operation process, TS, EAC, TD, and CDR are presented in Section 2.2.

To solve the issues of the widely used CP-based PLL described in Section 1, we propose the XOR-PLL by simply removing the LPF of prior XOR-gate-based PLL^[13], as illustrated in Fig. 3. Without the LPF, the VCO in prior PLL becomes the pulse-driven oscillator (PDO), namely its node voltages at N₁, N_2, and N₃ switch only when a low-level voltage pulse of V_C occurs. Thus, the static power of the oscillator as well as the whole PLL is omitted. This enables obvious size shrinkage and energy efficiency improvement concurrently.

The operation principle of the LPF-Less PLL is explained based on the simulated timing diagram depicted in Fig. 4 (f_carrier: 13.56 MHz). When BPSK_IN switches from 0 to 1, a V_C pulse generated, which makes I_C to be V_DD and causes N₂ goes to 1; then, N₃ goes to 0 to the trigger rising edges of PLL_OUT and N₁; after that, V_C goes to 1, N₁ and N₃ hold their voltage values till next transition of BPSK_IN; N₂ goes down slowly due to the leakage caused by nonzero voltage of N₁. The similar process is shown in Fig. 4 when BPSK_IN switches from 1 to 0. Note that it is essential to hold the voltages of N₁−N₃ when V_C is 1, so, the thick-oxide MOSFETs are used in the PDO to minimize the leakage. The PLL input phase offset can be compensated by the EAC and TS, as described in Section 2.2.

As explained before, the edge of PLL_OUT is trigged by the V_C pulse, which is generated by the transition of BPSK_IN. This indicates that PLL_OUT can track BPSK_IN in real time when a input phase transition, as demonstrated by the simulation results in Fig. 5. Hence, the data rate can be significantly improved compared to prior PLL-based BPSK modulators.

The schematics of TS, EAC, TD, and CDR are depicted in Figs. 6(a)−6(d), respectively, and the detailed operation process are explained in Fig. 7, including two parts: power-on calibration and normal operation.

Initially, the power-on signal POR goes from 0 to 1 to reset TS, EAC, TD, and CDR. After that, the TS block resets the initial phase of BPSK signal BPSK_SYN to lag the PLL signal PLL_SYN, and the delay of the digitally controlled delay line (DCDL, in Fig. 6(b)) in the EAC is reset to its minimal value with HOLD = 0; then the phase alignment calibration begins, and the counter starts to increase the DCDL delay step by step until BPSK_SYN begins to slightly lead PLL_DL (roughly aligned with each other). At that time, HOLD goes to 1 to hold the state of counter and phase/frequency detector (PFD)^[14], indicating the end of the power-on calibration.

After power-on calibration, our demodulator starts to operate normally. Without input data transition, TR keeps 0, as indicated in Fig. 6(c) and Fig. 7. When input data transition occurs, TR goes to 1. The rising edge of the TR is used to get D_OUT and CK_OUT through the CDR block^[7]. The main difference between DR_MAX = 0 and DR_MAX = 1 is TR signal, as compared in Figs. 7(a) and 7(b). When DR_MAX = 0 (see Fig. 7(a)), the delay between the data transition and the TR falling edge τ_TR is 2T_carrier (PLL output period). This is OK for the date rate ≤(f_carrier/4), but such TR cannot distinguish consecutive data transition at the data rate of (f_carrier/2). In the contrast, if DR_MAX = 1, TR pulse width can be reduced to t₂, as indicated in Fig. 6(c). Thus, τ_TR can be <2T_carrier by properly setting t₂ so that the modulated data (DATA_MOD) can be correctly demodulated (see D_DEMOD and D_OUT) at the maximum data rate of f_carrier/2, as illustrated in Fig. 7(b).

This demodulator can still operate at the data rate below f_carrier/2 if DR_MAX = 1, as indicated in Fig. 7(b). However, such mode cannot support the use of high-Q coils because the received input of the demodulator requires several cycles to invert its phase when data transition occurs. Hence, the phase difference between BPSK_SYN and PLL_DL lasts more than one carrier period. This means that one input data transition may generate more than one TR pulses when DR_MAX = 1, thus leading to wrong demodulated output, as demonstrated by the simulation results shown in Fig. 8(a). Alternately, if DR_MAX = 0, each data transition still generate one TR pulse, thus maintaining the correct function, as illustrated in Fig. 8(b).

In summary, our proposed BPSK demodulator can operate at a high data rate of f_carrier/2 with low-Q coils by selecting DR_MAX to be 1, and can also support high-Q coils at a lower data rate with DR_MAX = 0.

Fig. 9 exhibits our 40-nm CMOS prototype. The core area of our BPSK demodulator is only 0.0012 mm², of which only 0.000123 mm² (8.5 μm × 14.5μm) is occupied by the LPF-Less PLL. It is supplied by a 0.6-V supply voltage and operates at 13.56-MHz f_carrier. An on-chip BPSK modulator with a PRBS-7 generator was also implemented for function testing. Fig. 10 demonstrates the operation at its maximum data rate of 6.78 Mb/s (f_carrier/2). The dc power excluding output buffer for testing is 4.47 μW, corresponding to an energy efficiency of 0.66 pJ/bit.

We also measured the performance with high-Q coins (L: 2.6 μH, Q: 68.4)^[15] at the demodulator’s input, as the test setup shown in Fig. 11(a). The modulated BPSK signal is generated by an arbitrary function generator and a transmitter (TX) board, and transmitted to the receiver (RX) frond-end board through two coupled high-Q coils for our BPSK demodulator. Fig. 11(b) shows the measured results at the data rate of 1.695 Mb/s (f_carrier/2), demonstrating the correct function with high-Q coils.

Table 1 compare the performance of this work with other recently published BPSK demodulators. Compared to other PLL-based approaches, the core area of our work is at least 3.3 times smaller, and the data rate is at least 8 times higher with the best energy efficiency. When compared to other PLL-less BPSK demodulators, the area and energy efficiency of this work are also among the best reported to date with a comparable data rate, and this work supports the operation with high-Q coils.

This paper presents a PLL-based BPSK demodulator and demonstrated in a 40-nm CMOS process. Thanks to our proposed LPF-Less PLL, the core area is significantly shrunk with the concurrent improvement of the data rate and energy efficiency.