Researching | A 0.0012-mm2 0.66-pJ/bit BPSK demodulator incorporating a loop-filter-less PLL achieving the maximum data rate of fcarrier/2

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Journal of Semiconductors
Vol. 46, Issue 3, 032201 (2025)

A 0.0012-mm² 0.66-pJ/bit BPSK demodulator incorporating a loop-filter-less PLL achieving the maximum data rate of f_carrier/2

Xinyu Shen^1,2, Zhao Zhang^1,2,*, Jie Yang³, Jian Liu^1,2..., Nanjian Wu^1,2, Mohamad Sawan³ and Liyuan Liu^1,2|Show fewer author(s)

Author Affiliations

¹State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100049, China

²Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

³CenBRAIN Neurotech, School of Engineering, Westlake University, Hangzhou 310024, China

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DOI: 10.1088/1674-4926/24100022 Cite this Article

Xinyu Shen, Zhao Zhang, Jie Yang, Jian Liu, Nanjian Wu, Mohamad Sawan, Liyuan Liu. A 0.0012-mm² 0.66-pJ/bit BPSK demodulator incorporating a loop-filter-less PLL achieving the maximum data rate of f_carrier/2[J]. Journal of Semiconductors, 2025, 46(3): 032201 Copy Citation Text

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References

[1] S H Wang, Y K Huang, C Y Chen et al. Design of a bone-guided cochlear implant microsystem with monopolar biphasic multiple stimulations and evoked compound action potential acquisition and its in vivo verification. IEEE J Solid State Circuits, 56, 3062(2021).

[2] X H Qian, Y C Lee, J H Chang et al. Design and in vivo verification of a CMOS bone-guided cochlear implant microsystem. IEEE Trans Biomed Eng, 66, 3156(2019).

[3] Y Y Jia, U Guler, Y P Lai et al. 26.8 A trimodal wireless implantable neural interface system-on-chip. 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 414(2020).

[4] Y Park, S T Koh, J Lee et al. 33.7 A frequency-splitting-based wireless power and data transfer IC for neural prostheses with simultaneous 115mW power and 2.5Mb/s forward data delivery. 2021 IEEE International Solid-State Circuits Conference (ISSCC), 472(2021).

[5] Y M Hu, M Sawan. A fully integrated low-power BPSK demodulator for implantable medical devices. IEEE Trans Circuits Syst I Regul Pap, 52, 2552(2005).

[6] C H Cheng, P Y Tsai, T Y Yang et al. A fully integrated 16-channel closed-loop neural-prosthetic CMOS SoC with wireless power and bidirectional data telemetry for real-time efficient human epileptic seizure control. IEEE J Solid State Circuits, 53, 3314(2018).

[7] Y X Li, X Y Shen, Z Y Zhang et al. A 0.004-mm2 0.7-V 31.654-μW BPSK demodulator incorporating dual-path loop self-biased PLL. 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 569(2022).

[8] L Pan, M Y Chen, Y F Chen et al. An energy-autonomous power-and-data telemetry circuit with digital-assisted-PLL-based BPSK demodulator for implantable flexible electronics applications. IEEE Open J Circuits Syst, 2, 721(2021).

[9] H Cho, H Lee, J Bae et al. A 5.2 mW IEEE 802.15. 6 HBC standard compatible transceiver with power efficient delay-locked-loop based BPSK demodulator. IEEE J Solid State Circuits, 50, 2549(2015).

[10] C Y Lo, H C Hong. A 0.9 pJ/b, reference clock free, delay-based, all-digital coherent BPSK demodulator. IEEE Solid State Circuits Lett, 3, 498.

[11] B P Wilkerson, J K Kang. A low power BPSK demodulator for wireless implantable biomedical devices. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 626(2013).

[12] Z Zhang, G Zhu, C P Yue. A 0.25–0.4-V, sub-0.11-mW/GHz, 0.15–1.6-GHz PLL using an offset dual-path architecture with dynamic charge pumps. IEEE J Solid State Circuits, 56, 1871(2021).

[13] L Kong, B Razavi. A 2.4 GHz 4 mW integer-N inductorless RF synthesizer. IEEE J Solid State Circuits, 51, 626(2016).

[14] Z Zhang, J C Yang, L Y Liu et al. A 0.9–2.25-GHz sub-0.2-mW/GHz compact low-voltage low-power hybrid digital PLL with loop bandwidth-tracking technique. IEEE Trans Very Large Scale Integr VLSI Syst, 26, 933(2018).

[16] M Karimi, M H Maghami, M Faizollah et al. A noncoherent low-power high-data-rate BPSK demodulator and clock recovery circuit for implantable biomedical devices. 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings, 372(2014).

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Xinyu Shen, Zhao Zhang, Jie Yang, Jian Liu, Nanjian Wu, Mohamad Sawan, Liyuan Liu. A 0.0012-mm² 0.66-pJ/bit BPSK demodulator incorporating a loop-filter-less PLL achieving the maximum data rate of f_carrier/2[J]. Journal of Semiconductors, 2025, 46(3): 032201

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