Hongyi Wang, Wengang Tao, Yifan Lu, Yonggang Zhang, Songlei Huang, Jiaxiong Fang. Study of low-power readout circuit based on a programmable windowing IP core[J]. Infrared and Laser Engineering, 2023, 52(12): 20230241
- Infrared and Laser Engineering
- Vol. 52, Issue 12, 20230241 (2023)
Fig. 1. The system architecture of IRFPA ROIC with programmable windowing IP core
Fig. 2. Analog signal chain
Fig. 3. （a） Pixel unit circuit structure; （b） 2×2 pixel array layout
Fig. 4. （a） Power consumption control module and push-pull output structure; （b） The op-amp structure of push-pull output stage
Fig. 5. （a） Operating timing of the column-level output buffers; （b） Timing diagram for column-level time-selection technology
Fig. 6. Top-level logic for the programmable windowing digital IP core
Fig. 7. Arbitrary windowing function output simulation, readout area 8×8
Fig. 8. The layout of programmable arbitrary windowing digital IP core
Fig. 9. （a） The layout of 640×512 scale programmable arbitrary windowing IRFPA ROIC; （b） Die photograph of ROIC chip
Fig. 10. Test platform of the IRFPA ROIC chip and the FPA module
Fig. 11. Verification of programmable arbitrary windowing function. (a) Full-frame imaging; (b) Top left windowing 384×256; (c) Center windowing 256×256; (d) Bottom right windowing overflow test 128×128
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Table 1. The main performance parameters of the programmable arbitrary windowing IRFPA assembly
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