Infrared focal plane detectors are moving towards larger scale, higher frame rates, and higher levels of integration. In application scenarios such as high-speed target tracking and detection and region of interest imaging, the difficulty of high power consumption faced at high-speed readout needs to be addressed. As the spatial resolution of the infrared focal plane detectors has gradually increased to today's millions and even tens of millions of pixels, the size of the infrared focal plane arrays （IRFPA） has grown, and the need for high frame rate readout and random windowing has become increasingly urgent. At the same time, the increase in scale has also brought about a continuous increase in circuit power consumption, and the circuits that achieve these functions are becoming increasingly complex. The traditional design of digital readout integrated circuit (ROIC) modules from the transistor level is becoming increasingly difficult. Random windowing is an effective way to increase the IRFPA ROIC frame rate and enable the readout of regions of interest. As the need for increasingly complex IR detector customisation grows, the typical architecture of existing ROIC implemented at the chip level for random windowing has many limitations, such as long design cycles for customisation, poor scalability of different-sized arrays and the difficulty of achieving small cell sizes in terms of the occupied pixel area.For large-format IRFPA high frame rate applications, this paper proposes a programmable windowing IP core design (Fig.7) based on the digital IC design flow implementation and achieves ultra-low power optimisation of the 640×512 readout circuit column module by using a column-level time-selection technology (Fig.5). The pixel cell circuit contains a CTIA input stage, a double sample-and-hold structure and a follow output structure (Fig.3), that compromises the optimisation of area, noise, gain, etc. A low-noise, high-speed programmable arbitrary windowing 640×512 ROIC with pixel pitch 15 µm is designed and fabricated in 0.18 µm CMOS technology (Fig.10). The ROIC is coupled with a short-wave infrared InGaAs detector chip to form an FPA assembly and tested at room temperature.The infrared focal plane test system (Fig.11) consists of a DC power supply, a 5078 timing generator, a digital acquisition card, a blackbody light source and a dedicated PCB test board for the functional testing of the 640×512 scale InGaAs infrared focal plane detector assemblies with windowing. A row of pins was placed in front of the sensing area of the focal plane assembly for imaging to verify the circuit windowing function. The circuit function was verified in several typical application scenarios, such as full frame readout, upper left corner windowing, centre windowing and windowing address overflow, respectively, to obtain an IRFPA windowing image (Fig.12). The test results show that the entire 640×512 scale InGaAs IR detector assembly functions normally, and the programmable windowing digital IP core functions as expected, which can realise the specified area windowing and effectively improve the ROIC frame rate. The power consumption of the column-level output circuit mainly comes from the output buffer. The time-selection technology proposed in the paper effectively reduces the power consumption, in which the total power consumption of the whole assembly is less than 80 mW under the 3.3 V power supply. The power consumption of the column level is only 15 mW, and the readout rate reaches 15 MHz (Tab.1).In this paper, a programmable windowing digital IP core module design is proposed based on the digital IC design flow implementation, which can achieve high frame rate readout in windowing mode. This programmable windowing IP core uses a row-address-controlled windowing architecture, allowing the windowing core algorithm to be reused for different-sized IRFPA readout circuits with good scalability and no pixel area occupation. At the same time, to address the problem of high power consumption in high frame rate readout, a time-selection technology is used to optimise the ultra-low power consumption of the column-level module of the ROIC. The programmable windowing IP core layout is integrated with the analogue pixel array layout to achieve a scale of 640×512, 15 µm low-power, high-speed programmable arbitrary windowing IRFPA readout circuit based on a 0.18 µm CMOS process. The ROIC is coupled with a short-wave infrared InGaAs detector chip to form an FPA assembly and tested at room temperature. The results show that the time-selection technology effectively reduces the power consumption of the column-level circuit, the total power consumption of the circuit readout is less than 80 mW while the power consumption of the column-level is only 15 mW, and the readout rate reaches 15 MHz. The programmable windowing digital IP core functions properly, allowing for the readout of specified areas. The work in this paper provides the technical basis for subsequent large-scale small-pitch IRFPA high frame rate low power ROICs.