• Acta Physica Sinica
  • Vol. 69, Issue 17, 177103-1 (2020)
Yi-Xun Jiang1, Ming Qiao1、*, Wen-Ming Gao2, Xiao-Dong He2, Jun-Bo Feng1, Sen Zhang2, and Bo Zhang1
Author Affiliations
  • 1State Key Laboratory of Electronic Thin Film and Integrated Devices, University of Electronic Science and Technology of China, Chendu 610054, China
  • 2CSMC Technologies Corporation, Wuxi 214028, China
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    DOI: 10.7498/aps.69.20200359 Cite this Article
    Yi-Xun Jiang, Ming Qiao, Wen-Ming Gao, Xiao-Dong He, Jun-Bo Feng, Sen Zhang, Bo Zhang. A compact model of shield-gate trench MOSFET based on BSIM4[J]. Acta Physica Sinica, 2020, 69(17): 177103-1 Copy Citation Text show less

    Abstract

    Shield-gate trench MOSFET in a low-to-medium voltage range (12-250 V) plays a key role in the power conversion market due to its low power loss caused by the sheild-gate structure. In order to eliminate the faults resulting from the parasitic effects of the device and improve the conversion efficiency, the device model is indispensable in designing a circuit system. In this paper, a compact model of shield-gate trench MOSFET based on BSIM4 is proposed, including the DC model and the capacitance model. In the DC model, the basic MOSFET structure uses BSIM4, and the equivalent resistances of the basic MOSFET in series are divided into three parts. The equivalent resistance model of JFET region is established by using the electric potential difference between both ends for the first time, and the equivalent resistance model of electron diffusion region is also introduced, in order to solve the problem of current error caused by neglecting the source potential of JFET region. The equivalent resistance between drain and JFET region and the equivalent resistance of electron diffusion region both prove to be constant. In the capacitance model based on BSIM4, the model of shield-gate to drain capacitance is added to the model of drain to source capacitance, and the voltage bias between drain and gate in the model of gate to drain capacitance is modified into the potential difference between the node at the end of the gate-drift overlap region and the gate. Poisson equations are used to solve the electric potential of this node. Furthermore, the gate oxide thickness factor k1, the shield-gate oxide thickness factor k2, the equivalent length of gate-drift overlap Lovequ and the equivalent length of shield-gate LSHequ are introduced to redefine the position of gate and shield-gate, thereby simplifying the Poisson equations and ensuring the smoothness of the potential curve of the node. Comparison of the data from the simulation by using Verilog-A program with the test results from the experimental platform shows that the model simulation results fit well with the test data, Therefore, the proposed model is verified.
    Yi-Xun Jiang, Ming Qiao, Wen-Ming Gao, Xiao-Dong He, Jun-Bo Feng, Sen Zhang, Bo Zhang. A compact model of shield-gate trench MOSFET based on BSIM4[J]. Acta Physica Sinica, 2020, 69(17): 177103-1
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