• Microelectronics
  • Vol. 51, Issue 1, 64 (2021)
WU Wei1、2, DI Zhixiong1、2, CHEN Jinwei1、2, and FENG Quanyuan1、2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.200087 Cite this Article
    WU Wei, DI Zhixiong, CHEN Jinwei, FENG Quanyuan. An Overflow-Based Local Congestion Elimination Technique[J]. Microelectronics, 2021, 51(1): 64 Copy Citation Text show less
    References

    [1] ALPERT C J, LI Z, MOFFITT M D, et al. What makes a design difficult to route [C] // Proceed ACM ISPD. San Francisco, CA, USA. 2010: 7-12.

    [2] LI Z, ALPERT C J, NAM G J, et al. Guiding a physical design closure system to produce easier-to-route designs with more predictable timing [C] // Proceed DAC. San Francisco, CA, USA. 2012: 465-470.

    [3] SHI D, DAVOODI A. TraPL: track planning of local congestion for global routing [C] // Proceed DAC. Austin, TX, USA. 2017: 1-6.

    [4] HAN Y, ANCAJAS D M, CHAKRABORTY K, et al. Exploring high-throughput computing paradigm for global rouing [J]. IEEE Trans Very Large Scale Integr Syst, 2014, 22(1): 155-167.

    [5] WANG L C. Experience of data analytics in EDA and test-principles, promises, and challendges [J]. IEEE Trans Comput-Aided Des Integr Circ Syst, 2017, 36(6): 885-898.

    [6] TABRIZI A F, RAKAI L, DARAV N K, et al. A machine learning framework to identify detailed routing short violations from a placed netlist [C] // Proceed DAC. San Francisco, CA, USA. 2018: 1-6.

    [7] CHAN W T J, HO P H, KAHNG A B, et al. Routability optimization for industrial designs at sub-14 nm process nodes using machine learning [C] // Proceed ACM ISPD. Portland, OR, USA. 2017: 15-21.

    [9] BODINE F. Reducing cell placement congestion using targeted pattern halos [C] // Proceed SNUG. Boston, MA, USA. 2014: 23-26.

    WU Wei, DI Zhixiong, CHEN Jinwei, FENG Quanyuan. An Overflow-Based Local Congestion Elimination Technique[J]. Microelectronics, 2021, 51(1): 64
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