Loss reduction is considered as the most fundamental and critical priority in the development of on-chip photonic integrated circuits (PICs), and tremendous efforts have been made to develop ultralow-loss optical waveguides in the past decades. Many PICs used for true-time-delay lines [1–6], optical gyroscopes [7,8], optical coherence tomography [9,10], and microwave photonics beam-forming [11,12] often require very long on-chip waveguides, and hence various low-loss optical waveguides have been demonstrated on different platforms such as ${\mathrm{Si}}_3{\mathrm{N}}_4$ [2,10], ${\mathrm{SiO}}_2$ [13,14], and silicon [4,15–20]. Though ${\mathrm{Si}}_3{\mathrm{N}}_4$ and ${\mathrm{SiO}}_2$ optical waveguides exhibit low losses down to $\sim 1\mathrm{dB}/\mathrm{m}$ [2] and $\sim 0.1\mathrm{dB}/\mathrm{m}$ [14], their bending radii usually have to be as large as hundreds of micrometers or even millimeters, which prevents the realization of on-chip high integration density. In contrast, by taking advantage of the complementary metal–oxide semiconductor (CMOS) compatibility as well as high index-contrast $\mathrm{\Delta }n$ between the silicon core and silica cladding, silicon-on-insulator (SOI) nanophotonic waveguides have very strong optical field confinement to have microscale bending radii, which is gaining intensive interest for enabling ultra-compact photonic integrated devices and circuits [21–23]. On the other hand, however, the enhancement of light confinement strongly increases the interaction between the optical modal field and the rough etched sidewalls [24]. This might introduce a high scattering loss, which is proportional to ${(\mathrm{\Delta }n)}^3$ [15,25].

Basically speaking, currently there are two typical methods to reduce the scattering losses in optical waveguides. One is to smoothen the waveguide sidewalls (characterized by the mean square deviation ${\sigma }^2$ of the sidewall roughness) by improving the fabrication processes or introducing some specific processes, such as an oxidation-based etchless process [16], chemical oxidation [17], anisotropic etching [15], and post-processing [18,19]. For instance, an etchless process based on selective thermal oxidation was developed to fabricate a silicon photonic waveguide with a low loss of 0.3 dB/cm [16]. However, these specific processes are usually incompatible with the multi-project-wafer (MPW) foundry for silicon photonics, and thus they are not easy to use for further photonic integration. The other one is to decrease the interaction of the optical modal field with the rough sidewalls by introducing a shallowly etched ridge or ultrathin core region [4,20]. For example, a shallowly etched SOI ridge waveguide with a cross section of $0.25\mathrm{\mu m}\times 2\mathrm{\mu m}$ and an etching depth of 50 nm was employed, and the propagation loss was about 0.274 dB/cm [20]. Later, an ultrathin silicon photonic waveguide with a 60-nm-thick core region was also demonstrated with a reduced propagation loss of 0.61 dB/cm [4]. As it might be noticed, these silicon photonic waveguides are not compatible with standard 220-nm-thick silicon strip waveguides. Furthermore, since their mode confinement becomes very weak, the bending radii are required to be as large as several tens [4] or hundreds [20] of micrometers, while the decoupling separation between adjacent waveguides is also pretty large. The large bending radius requires a sufficient footprint, and as a result, the compactness of the delay lines is realized with difficulty [2,10,13,14,20]. To minimize the footprints of waveguide spirals, one should reduce the gap $W_g$ between adjacent waveguides as well as the radius of the S-bend in the middle. As a result, it is still challenging to achieve long delay lines with low losses, high compactness, and broad bandwidths by using 220-nm-thick silicon strip waveguides.

In this paper, we propose and realize an ultralow-loss and ultra-compact 220-nm-thick silicon strip waveguide spiral fabricated with standard MPW processes. Here the silicon strip waveguide is designed with a broadened core region beyond the single-mode regime. In this way, the field amplitude at the sidewalls can be reduced significantly, and thus the scattering loss is reduced greatly. Particularly, to be compact with negligible losses as well as high-order mode excitation, a tapered Euler-curve S-bend is introduced for the waveguide spiral. With such low-loss and compact waveguide spirals, a 10-bit tunable optical true-time-delay line on silicon is realized with a time delay as long as 5120 ps for the first time.

Figure 1(a) shows the configuration of the proposed silicon photonic waveguide spiral, which consists of single-mode input/output waveguides, two bent waveguide tapers, two multimode Archimedean spiral waveguides, and a tapered Euler-curve S-bend in the middle. The bent waveguide tapers should be long enough to adiabatically connect the narrow input/output waveguide and the broadened Archimedean spiral waveguide, so that the fundamental-mode loss and the higher-order mode excitation ratio is negligible. Usually, the length of the bent waveguide tapers is chosen as $R\pi /2$, where $R$ is the maximal bending radius of the Archimedean spiral. The Archimedean spiral presents a gradually varied bend radius and uniform gap widths. This makes the Archimedean spiral very attractive to achieve adiabatic light propagation of the fundamental mode in a multimode waveguide without any higher-order mode excitation even when the radius is gradually reduced to be small. In contrast, waveguide spirals with normal circular bend usually require large bending radii to overcome the mode mismatch at the junction between the circular bends with different radii. For this tapered Euler-curve S-bend, the curvature radius is varied gradually from the maximum $R_{\max }$ to the minimum $R_{\min }$ and back to $R_{\max }$, while the core width is varied gradually from the maximum $W_m$ to the minimum $W_S$, as shown in Fig. 1(b). In this way, the transition loss and the intermode cross talk introduced by the junction in the middle of the S-bend can be minimized possibly even when the maximal bending radius $R_{\max }$ is not very large.

To evaluate the loss due to the scattering at the waveguide interfaces, which is the major loss source, a three-dimensional volume current method was used for modeling [26–28]. In this way, the scattering is modeled as an equivalent polarization volume current density. Figures 2(a)–2(c) show the calculated losses due to the top/bottom surface scattering and sidewall scattering, as well as the total scattering loss, respectively. Apparently, the scattering loss decreases greatly as the roughness $\sigma$ is reduced. One should note that the sidewall roughness is limited by the fabrication processes, while the top/bottom surface roughness is determined by the SOI wafer quality.

For standard MPW processes, the sidewall roughness ${\sigma }_{\mathrm{sidewall}}$ due to an optimized dry etching of the core is typically around 1–10 nm [26–31], while the top/bottom surface roughness ${\sigma }_{\mathrm{surface}}$ resulting from polished/deposited thin films is usually $\sim 0.3\mathrm{nm}$ [28,29], and their correlation lengths usually are around 50 nm and 30 nm [26–31], respectively. For the popular 450-nm-wide silicon photonic waveguide, the top/bottom surface scattering loss is usually about $\sim 0.1\mathrm{dB}/\mathrm{cm}$, while the sidewall scattering loss is usually about several dB/cm. In this case, it is no doubt that the scattering at the sidewalls is the major loss source. As shown in Fig. 2(a), the loss due to the scattering at the top/bottom surfaces first increases to a maximum (around $W_{\mathrm{co}}=1\mathrm{\mu m}$) and then decreases slightly when the core width increases from 0.45 to 3 μm. This can be explained as follows. When the core width increases, the areas of the top/bottom surfaces increase, which tends to introduce an increase of the scattering loss. Meanwhile, the mode confinement in the core region becomes enhanced, and thus the field amplitudes at the top/bottom surfaces decrease, which tends to decrease the scattering loss. The core-width dependence of the top/bottom surface scattering loss shown in Fig. 2(a) results from the balance of these two factors. In contrast, the loss due to the scattering at the sidewalls can be reduced exponentially as the core width increases, which is due to the significant decrease in field amplitudes at the sidewalls, as shown in Fig. 2(b). For example, the scattering loss is reduced from 4.2 to 0.042 dB/cm in theory when the core width is increased from 0.45 to 2 μm when ${\sigma }_{\mathrm{sidewall}}=4\mathrm{nm}$. As a result, the scattering losses from the top/bottom surfaces might become the major factor when the core width is sufficiently large. Figure 2(c) shows the calculated total scattering loss when assuming the top/bottom surface roughness ${\sigma }_{\mathrm{surface}}=0.4\mathrm{nm}$. It can be seen that the total scattering loss becomes insensitive to the core width when $W_{\mathrm{co}}>2\mathrm{\mu m}$. On the other hand, it is usually not desired to have a very wide core region to avoid the difficulty of mode manipulation (such as higher-mode excitation). Therefore, in this paper, we choose $W_m=2\mathrm{\mu m}$ in the design of the present waveguide spirals. Correspondingly, the total scattering loss for such a waveguide is about $\sim 0.25\mathrm{dB}/\mathrm{cm}$, which is 10 times less than that for a 450-nm-wide silicon photonic waveguide.

As another key factor to minimize the footprint of the waveguide spiral, the gap width $W_{\mathrm{gap}}$ between two adjacent waveguides should be as small as possible without evanescent coupling. As it is well known, the coupling length $L_c$ is calculated by using the following equation [32]: $$L_c=\frac{\lambda }{2(n_{\mathrm{eff},{\mathrm{TE}}_0}-n_{\mathrm{eff},{\mathrm{TE}}_1})},$$(1)where $\lambda$ is the wavelength, and $n_{\mathrm{eff},{\mathrm{TE}}_0}$ and $n_{\mathrm{eff},{\mathrm{TE}}_1}$ are the effective indices of the ${\mathrm{TE}}_0$ and ${\mathrm{TE}}_1$ supermodes. Here the effective indices are calculated using the finite element method (FEM) mode solver. The coupling length calculated from Eq. (1) is demonstrated as a function of the gap width of the spiral waveguides, as shown in Fig. 3. Since the waveguide spiral is long in our case, the waveguide gap is chosen as $W_{\mathrm{gap}}=1.5\mathrm{\mu m}$, and the corresponding coupling length is up to 2400 m, which is sufficient to avoid the cross talk from the adjacent waveguide.

As is well known, the design of a broadened waveguide bend should be careful to avoid excitation of the higher-order mode when light carried by the fundamental mode propagates along the multimode waveguide spiral. Notice that the S-bend in the middle is one of the keys for the waveguide spiral design because there is an abrupt change of the bending radii from $R$ to $-R$. To guarantee ultralow bending losses and negligible higher-order-mode excitation, here we propose a tapered Euler-curve S-bend defined as [33–35] $$\frac{\mathrm{d}\theta }{\mathrm{d}L}=\frac{1}{R}=\frac{L}{A^2}+\frac{1}{R_{\max }},$$(2)where $L$ is the curve length, $A$ is a constant given by $A={[L_{\max }/(1/R_{\min }-1/R_{\max })]}^{1/2}$, and $L_{\max }$ is the total length of the waveguide bend. In general, the maximal radius $R_{\max }$ and the minimal radius $R_{\min }$ should be as small as possible to shrink the S-bend footprint. As the core width $W_m$ is fixed as 2 μm, the radii $(R_{\max },R_{\min })$ and the width $W_s$ should comply with the design rule as follows: (1) the maximal radius $R_{\max }$ should be equal to the minimal radius of the designed Archimedean spiral waveguide; (2) the maximal radius $R_{\max }$ and the width $W_s$ should be optimized to void any notable mode mismatch at the abrupt junction in the middle; (3) the minimal radius $R_{\min }$ should be chosen to make the effective diameter $D_{\mathrm{eff}}$ [as defined in Fig. 1(b)] of the 180° Euler-curve bend equal to the radius of the inner circle of the Archimedean spiral waveguide.

Figures 4(a) and 4(b) show the calculated excess loss and intermode cross talk as the radius $R_{\max }$ and the core width $W_s$ vary. As it can be seen, one can achieve low excess losses and low cross talk by choosing a sufficiently large radius $R_{\max }$ and a narrow width $W_s$. For example, the excess loss is less than 0.01 dB, and the intermode cross talk is negligibly low ($<\text{−}30\mathrm{dB}$) when $W_s<0.6\mathrm{\mu m}$ and $R_{\max }>20\mathrm{\mu m}$ (as shown in the marked area). As an example, we choose $R_{\max }=25\mathrm{\mu m}$ and $W_s=0.6\mathrm{\mu m}$ by making a trade-off between the loss and the footprint compactness. Accordingly, the total loss is less than 0.01 dB, and the intermode cross talk is less than $-30\mathrm{dB}$. The radius $R_{\min }$ is chosen as 10 μm so that one has $D_{\mathrm{eff}}=R_{\max }$. The footprint of this designed S-bend is as small as $52\mathrm{\mu m}\times 32\mathrm{\mu m}$. In addition, the bend radii of the Archimedean spiral and Euler bend are elaborately designed to be the same at the junction connecting them. Therefore, there is no transition loss and no intermode cross talk when light goes through the junction.

Figures 4(c) and 4(e) show the simulated light propagation in the designed tapered Euler-curve S-bend and the calculated mode-excitation ratios monitored at the output port. Here a three-dimensional finite-difference time-domain (3D-FDTD) method was used in the simulation. From Fig. 4(c), it can be seen that the launched ${\mathrm{TE}}_0$ mode propagates smoothly along the present tapered Euler-curve S-bend, and no multimode interference is observed, indicating that the excess losses and the intermode cross talk are low. From Fig. 4(e), it can be seen that the estimated excess loss is $<0.016\mathrm{dB}$, and the intermode cross talk is $<\text{−}26\mathrm{dB}$ in the wavelength band from 1500 to 1600 nm. In contrast, for a regular arc S-bend with the same footprint of $52\mathrm{\mu m}\times 32\mathrm{\mu m}$, significant multimode interference occurs when the ${\mathrm{TE}}_0$ mode is launched, as shown in Fig. 4(d). From Fig. 4(f), which shows the calculated mode excitation ratios monitored at the output port, the estimated intermode cross talk is as high as $-2.3\mathrm{dB}$. Therefore, it can be seen that the present tapered Euler-curve S-bend works very well with low-loss and low-cross-talk light propagation of the fundamental mode even when the footprint is compact.

The designed silicon photonic waveguide spirals were fabricated by the MPW foundry (Institute of Microelectronics, China) with the standard processes of deep UV lithography and inductively coupled plasma dry-etching. A 1-μm-thick silica thin film was deposited on the top as the upper-cladding. There are seven samples of chips, and each has five waveguide spirals with different lengths of $L=5$, 10, 20, 50, and 100 cm for the design with $W_m=2\mathrm{\mu m}$. For the present 5-cm-long waveguide spiral, the maximal bending radius is about 240 μm. For any waveguide spiral longer than 5 cm (e.g., $L=10$, 20, 50, and 100 cm here), the additional part has a bending radius of $>240\mathrm{\mu m}$, in which case, the bend behaves like a straight waveguide with the same core width according to the theoretical analysis. As a result, it is expected that the total propagation losses of these waveguide spirals increase linearly as the total length increases from 5 to 100 cm. In this way, one can estimate the propagation loss by using the cutback method [2,20]. The waveguide spirals with different core widths of $W_m=0.45$ and 1.6 μm are also fabricated on the same chip to give a comparison.

Figure 5(a) shows the microscope image of the fabricated 50-cm-long silicon photonic waveguide spiral. The setup with an amplified spontaneous emission (ASE) source and an optical spectrum analyzer (OSA) was used for measuring the transmissions of these waveguide spirals. Here grating couplers were used for efficient chip–fiber coupling. The measured transmissions in the wavelength range of 1530–1580 nm are shown in Fig. 5(b). It can be seen that the waveguide loss is almost wavelength insensitive in the C-band, which indicates that there is no multimode interference occurring in the waveguide spirals. The measured waveguide losses at 1550 nm for seven chips are given in Fig. 5(c). It can be seen that the waveguide loss increases linearly with propagation distance. The data fitting shows the measured waveguide loss is about $\sim 0.28\mathrm{dB}/\mathrm{cm}$ for the case with $W_m=2\mathrm{\mu m}$. In contrast, the measured losses for the waveguide spirals with $W_m=0.45$ and 1.6 μm on the same chips are 5.5 and 0.38 dB/cm, respectively. Figure 5(d) shows the data fitting for the measured waveguide loss by the theoretical results from the three-dimensional volume current method [28] as the core width varies. It can be seen that the estimated roughness values of ${\sigma }_{\mathrm{sidewall}}$ and ${\sigma }_{\mathrm{surface}}$ are about 4.6 and 0.42 nm, respectively, which is consistent with the characterization result for the wafer surfaces and waveguide sidewalls.

The present waveguide spirals are further used to develop an $n$-bit tunable optical true-time-delay line on silicon, as shown in Figs. 6(a) and 6(b). Here the present 10 binary-delay stages are realized by integrating 11 $2\times 2$ Mach–Zehnder (MZ) silicon-photonic switches and 10 waveguide spirals with the time delays of $\mathrm{\Delta }\tau ,2\mathrm{\Delta }\tau ,4\mathrm{\Delta }\tau ,\dots$, and $2^9\mathrm{\Delta }\tau$, where the time delay $\mathrm{\Delta }\tau$ is about 10 ps. The lengths of the spirals for time delays of $\mathrm{\Delta }\tau$ and $2^9\mathrm{\Delta }\tau$ are 820 μm and 0.417 m, respectively. Their footprints are, respectively, $0.006{\mathrm{mm}}^2$ and $2.14{\mathrm{mm}}^2$. Here we used the $2\times 2$ thermo-optic MZ switch reported in our previous work [36]. In particular, these MZ switches have broadened phase shifters with lowered random phase errors, improved fabrication tolerance, and reduced power consumption for phase compensation. In the experiment, a pulse generated by a femtosecond laser (EFLA0222, Langyan) at 1550 nm is launched to the delay line system and received by a wide-bandwidth oscilloscope (Infiniium DCA-X 86100D, Keysight Technologies). The MZ switches are switched thermally by heating their micro-heaters controlled by a multichannel voltage source (XPOW-40AX-CCvCV-U, Nicslab). Figure 6(c) shows the measured optical output waveforms with the time delay varying from 10 to 5120 ps, which is the longest broadband tunable time delay on a silicon chip with the smallest footprint of $2.2\mathrm{mm}\times 5.9\mathrm{mm}$.

Table 1 gives a summary of on-chip tunable optical delay lines reported up to now. In particular, here only broadband time-delay lines are taken into account. Owing to the strong mode confinement, the propagation loss of regular silicon photonic waveguide spirals is usually as high as 2–3 dB/cm [1,5], which can be reduced to 0.6 dB/cm by introducing special thin silicon photonic waveguides or to 0.9 dB/cm by shallow etching to ridge-type waveguides as demonstrated in Refs. [3,4]. In contrast, our proposed silicon waveguide spiral has a propagation as low as 0.28 dB/cm and a minimal bending radius as compact as 10 μm, which makes it possible to realize a long time delay (e.g., 5.12 ns), a high resolution (e.g., 10 ps), as well as a compact footprint (e.g., $12.98{\mathrm{mm}}^2$). More importantly, the proposed silicon waveguide spiral and the time-delay chip can be fabricated with a simple single-etching process provided by a standard MPW foundry. Therefore, it is very easy to achieve arrayed optical time-delay lines for realizing complicated on-chip systems.Table 1.

Performance Comparison of On-Chip Tunable Delay Lines Based on Silicon-on-Insulator Waveguides^a

In summary, we have proposed and demonstrated a novel silicon photonic waveguide spiral consisting of single-mode input/output waveguides, two bent waveguide tapers, two broadened Archimedean spiral waveguides, and a tapered Euler-curve S-bend in the middle. The core width of the Archimedean spiral waveguides is chosen optimally to be $W_m=2\mathrm{\mu m}$ according to the analyses of the scattering loss, in which way the scattering loss at the sidewalls has been reduced greatly. The tapered Euler-curve S-bend inserted in the middle has been designed carefully to minimize the bending loss as well as the higher-order-mode excitation even for a compact waveguide spiral. The measured propagation loss is about 0.28 dB/cm, which is consistent with our theoretical model. Finally, an on-chip 10-bit tunable optical time delay has been designed and fabricated on the same chip, demonstrating a time delay as long as 5120 ps with a fine resolution of 10 ps. To the best of our knowledge, this is the first silicon chip with a long delay line up to 100 cm and a broadband time delay up to 5120 ps, owing to the low loss and compact footprint of the proposed waveguide spiral with a tapered Euler-curve S-bend. More importantly, all the waveguides/structures can be fabricated with a simple single-etching process by a standard MPW foundry, which makes it possible to be integrated monolithically with on-chip light sources, amplifiers [37], as well as photodetectors [38]. This provides an excellent option potentially in many applications in the future, such as true-time-delay lines [1–6], on-chip programmable systems [39], photonic beamformers [11], and data centers [40].