A 4-channel 16 bit 250 MS/s A/D converter was designed in a 0.18 μm CMOS process. In the converter, a time interleaved structure combined with pipelined structure was adopted, which consisted of reference, clock and digital correction units. The chip tested results showed that the dynamic specification achieved a SNR of 73 dBFS and a SFDR of 90 dBFS with digital calibration. The ADC channel power was 0.25 W, and the corresponding figure-of-merit (FoM) was 22 fJ/(conv·step).