Author Affiliations
1School of Environmental Science and Optoelectronic Technology, University of Science and Technology of China, Hefei, Anhui 230026, China2Anhui Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Hefei, Anhui 230031, Chinashow less
Fig. 1. Block diagram of cloud camera electronics system
Fig. 2. Three-level pulse signal driving circuit
Fig. 3. Simulation diagram of three-level pulse signal
Fig. 4. Driving circuit of electronic shutter
Fig. 5. Frame transfer timing, pixel readout timing, and electronic shutter timing. (a) Frame transfer timing; (b) pixel readout timing; (c) electronic shutter timing
Fig. 6. Vertical clock, horizontal clock and reset signal,and electronic shutter. (a) Vertical clock; (b) horizontal clock and reset signal; (c) electronic shutter
Fig. 7. SDRAM initialization process, and diagram of working state transition. (a) SDRAM initialization process; (b) diagram of working state transition
Fig. 8. CCD data acquisition and storage IP core
Fig. 9. Block diagram of performance test
Fig. 10. Camera performance test site
Fig. 11. Measurement results of dark current noise
Fig. 12. Relationship between output signal value and exposure time
Description | Signal | Level | Voltage | Equivalent capacitance /nF |
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| | High | 12 V | | Vertical clock | V1T/V1B | Mid | 0 V | 43 | | | Low | -8 V | | | V2T/V2B | High | 0 V | | Vertical clock | V3T/V3B | Low | -8 V | 43 | | V4T/V4B | | | | Horizontal clock | H1Sα/ H2Sα | High | 0 V | | | | Low | -5 V | 0.28 | Horizontal clock | H1Bα/ H2Bα | High | 0 V | | | | Low | -5 V | 0.19 | Horizontal clock | H2SLα | High | 0 V | | | | Low | -5 V | 0.02 | Reset gate | Rα | High | 3 V | | | | Low | -2 V | 0.016 | Electronic shutter | SUB | High | VSET | | | | Low | VSUB | 3 |
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Table 1. CCD drive signal levels and equivalent capacitances
T /ms | 7 | 10 | 15 | 20 | 25 | 30 | 35 | 40 | 50 | 60 | 70 |
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SNR | 20.5 | 24.5 | 37.1 | 43.9 | 52.3 | 68.3 | 74.7 | 76.8 | 102.2 | 113.8 | 128.1 |
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Table 2. Camera SNR at different exposure time