• Optical Instruments
  • Vol. 46, Issue 5, 31 (2024)
Qifan JIA1, Xuanhong JIN1,*, Pengcheng XIAO2, and Hangyu HE1
Author Affiliations
  • 1School of Optical-EleCtrical and Computer Engineering, University of Shanghai for Science and Technology, Shanghai 200093
  • 2. School of Microelectronics Fudan University, Shanghai 201203, China
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    DOI: 10.3969/j.issn.1005-5630.202310260120 Cite this Article
    Qifan JIA, Xuanhong JIN, Pengcheng XIAO, Hangyu HE. Design of ATE data storage and transmission system for optical chip testing[J]. Optical Instruments, 2024, 46(5): 31 Copy Citation Text show less
    References

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    [8] WANG X D, SHEN L Y, JIA M. The design optimization of DDR3 controller based on FPGA[C]Proceedings of the 2017 International Conference on Communications, Signal Processing, Systems. Singape: Springer, 2019: 17441750.

    [9] YI J H, WANG M F, BAI L D. Design of DDR3 SDRAM read-write controller based on FPGA[J]. Journal of Physics:Conference Series, 1846, 012046(2021).

    [14] VERMA S, DABARE A S. Understing clock domain crossing issues[EBOL]. [2007−12−24]. https:www.designreuse.comarticles17372clockdomaincrossing.html.

    Qifan JIA, Xuanhong JIN, Pengcheng XIAO, Hangyu HE. Design of ATE data storage and transmission system for optical chip testing[J]. Optical Instruments, 2024, 46(5): 31
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