[8] WANG X D, SHEN L Y, JIA M. The design optimization of DDR3 controller based on FPGA[C]Proceedings of the 2017 International Conference on Communications, Signal Processing, Systems. Singape: Springer, 2019: 17441750.
[14] VERMA S, DABARE A S. Understing clock domain crossing issues[EBOL]. [2007−12−24]. https:www.designreuse.comarticles17372clockdomaincrossing.html.