Qifan JIA, Xuanhong JIN, Pengcheng XIAO, Hangyu HE. Design of ATE data storage and transmission system for optical chip testing[J]. Optical Instruments, 2024, 46(5): 31
- Optical Instruments
- Vol. 46, Issue 5, 31 (2024)
Fig. 1. ATE structure block
Fig. 2. GPMC synchronous burst write timing in address/data multiplexing mode
Fig. 3. Embedded system workflow
Fig. 4. Signal offset in FPGA
Fig. 5. Control signal latch circuit
Fig. 6. Schematic diagram of GPMC interface module
Fig. 7. MIG_controller state diagram
Fig. 8. System implementation and verification platform
Fig. 9. Verify the write function of the system
Fig. 10. Verification of read data and storage function
Fig. 11. Waveform of GPMC writing selection signal
Fig. 12. Waveforms of reading selection with waiting
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Table 1. System testing results
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