Aiming at the problems of the traditional four-phase clock generator circuit, such as the overlapping of clock waveform signals and the leakage of charge pump, a new four-phase clock generator circuit with adjustable duty cycle is proposed. The circuit added a delay unit module between the clock signals that may overlap in each two phases, and adjusted the duty cycle of the output clock signal by controlling the delay time to avoid the overlap of the clock. Additionally, the delay unit was adapted to realize the controllable delay under the condition of external bias voltage. The simulation results based on a 55 nm CMOS process show that the four-phase clock generator circuit can output four-phase non-overlap clock signal stably in the clock input frequency range of 10-50 MHz, and can drive the 10-stage charge pump to pump 112 V efficiently at a supply voltage of 12 V. The tested results obtained from fabricated circuits show that the four-phase clock generator circuit can produce non-overlapping four-phase clock waveforms, and the clock output phase can meet the driving requirements of the charge pump.