• Journal of Semiconductors
  • Vol. 45, Issue 11, 111301 (2024)
Chao Ma, Weizhong Chen, Teng Liu, Wentong Zhang, and Bo Zhang*
Author Affiliations
  • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
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    DOI: 10.1088/1674-4926/24050003 Cite this Article
    Chao Ma, Weizhong Chen, Teng Liu, Wentong Zhang, Bo Zhang. Recent developments in superjunction power devices[J]. Journal of Semiconductors, 2024, 45(11): 111301 Copy Citation Text show less
    References

    [1] H Chenming. Optimum doping profile for minimum ohmic resistance and high-breakdown voltage. IEEE Trans Electron Devices, 26, 243(1979).

    [2] X B Chen. Semiconductor power devices with alternating conductivity type high-voltage breakdown regions, 1, 1(1993).

    [3] T Fujihira. Theory of Semiconductor Superjunction Devices. Jpn J Appl Phys, 36, 6254(1997).

    [4] L Lorenz, G Deboy, A Knapp et al. COOLMOS/sup TM/-a new milestone in high voltage power MOS, 3(1999).

    [5] P M Shenoy, A Bhalla, G M Dolny. Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET, 99(1999).

    [6] X B Chen, P A Mawby, Board K et al. Theory of a novel voltage-sustaining layer for power devices. Microelectronics J, 29, 1005(1998).

    [7] A G M Strollo, E Napoli. Optimal ON-resistance versus breakdown voltage tradeoff in superjunction power devices: a novel analytical model. IEEE Trans Electron Devices, 48, 2161(2001).

    [8] W T Zhang, B Zhang, M Qiao et al. Optimization and new structure of super junction with isolator layer. IEEE Trans Electron Devices, 64, 217(2017).

    [9] W T Zhang, B Zhang, M Qiao et al. The RON, min of Balanced Symmetric Vertical Super Junction Based on R-well Model. IEEE Trans Electron Devices, 64, 224(2017).

    [10] W Zhang, K Zhang, L Wu et al. The minimum specific on-resistance of 3-D superjunction devices. IEEE Trans Electron Devices, 70, 1206(2023).

    [11] H Kang, F Udrea. Theory of 3-D superjunction MOSFET. IEEE Trans Electron Devices, 66, 5254(2019).

    [12] X B Chen, H Yang, M Cheng. New "silicon limit" of power devices. Solid State Electron, 46, 1185(2002).

    [13] D Disney, G Dolny. JFET depletion in super junction devices, 157(2008).

    [14] X Chen. Microelectronic devices. 4th ed. Beijing: Publishing House of Electronics Industry, 1, 1(2018).

    [15] E K Liu, B S Zhu, J S Luo. Semiconductor physics. 8th ed. Beijing: Publishing House of Electronics Industry, 1, 1(2023).

    [16] E K Liu, B S Zhu, J S Luo. Semiconductor physics. 7th ed. Beijing: Publishing House of Electronics Industry, 1, 1(2017).

    [17] C Wang, X Li, L Li et al. Performance limit and design guideline of 4H-SiC superjunction devices considering anisotropy of impact ionization. IEEE Electron Device Lett, 43, 2025(2022).

    [18] L Yu, K Sheng. Modeling and optimal device design for 4H-SiC super-junction devices. IEEE Trans Electron Devices, 55, 1961(2008).

    [19] X Li, L Li, K Xie et al. Charge imbalance tolerance of 4H-SiC superjunction devices featuring breakdown path variation. IEEE Electron Device Lett, 44, 1044(2023).

    [20] T Hatakeyama, J Nishio, C Ota et al. Physical modeling and scaling properties of 4H-SiC power devices, 171(2005).

    [21] E Platania, Chen Z, Chimento F et al. A physics-based model for a SiC JFET accounting for electric-field-dependent mobility. IEEE Trans Industry Applications, 47, 199(2011).

    [22] N He, S Zhang, X Zhu et al. A 0. 25μm 700V BCD technology with ultra-low specific on-resistance SJ-LDMOS, 419(2020).

    [23] N He, S Zhang, H Wang et al. Ultra-high voltage BCD technology integrated 1000 V 3-D split-superjunction devices, 305(2022).

    [24] M Antoniou, F Udrea, F Bauer. The superjunction insulated gate bipolar transistor optimization and modeling. IEEE Trans Electron Devices, 57, 594(2010).

    [25] N Fujishima, Y Yano, G Tada et al. N-ch IGBT with high reverse blocking capability for multipoint differential line drivers, 70(1991).

    [26] Y Wu, Z Li, J Pan et al. 650 V super-junction insulated gate bipolar transistor based on 45 μm ultrathin wafer technology. IEEE Electron Device Lett, 43, 592(2022).

    [27] H Kang, F Udrea. Material limit of power devices—applied to asymmetric 2-D superjunction MOSFET. IEEE Trans on Electron Devices, 65, 3326(2018).

    [29] S G Nassif-khalil, C A T Salama. Super junction LDMOST in silicon-on-sapphire technology (SJ-LDMOST), 81(2002).

    [30] B Zhang, W T Zhang, Z J Li et al. Equivalent substrate model for lateral super junction device. IEEE Trans Electron Devices, 61, 525(2014).

    [31] B Zhang, L Chen, J Wu et al. SLOP-LDMOS-a novel super-junction concept LDMOS and its experimental demonstration, 1402(2005).

    [32] B Zhang, W Wang, W Chen et al. High-voltage LDMOS with charge-balanced surface low on-resistance path layer. IEEE Electron Device Lett, 30, 849(2009).

    [33] I Y Park, C Salama. CMOS compatible super junction LDMOST with n-buffer layer, 163(2005).

    [34] W T Zhang, Z Y Zhan, Y Yu et al. Novel superjunction LDMOS (>950 V) with a thin layer SOI. IEEE Electron Device Lett, 38, 1555(2017).

    [35] S G Nassif-Khalil, Z L Hou, C A T Salama. SJ/RESURF LDMOST. IEEE Trans Electron Devices, 51, 1185(2004).

    [36] R NG, F UDREA, K SHENG et al. Lateral unbalanced super junction (USJ)/3D-RESURF for high breakdown voltage on SOI, 395(2001).

    [37] Y Guo, J Yao, B Zhang et al. Variation of lateral width technique in soi high-voltage lateral double-diffused metal–oxide–semiconductor transistors using high-K dielectric. IEEE Electron Device Lett, 36, 262(2015).

    [38] W Zhang, F Tian, Y Liu et al. Experiments of sub-micron superjunction devices with ultra-low specific on-resistance. IEEE Electron Device Lett, 44, 1160(2023).

    [39] X Zhong, B Wang, J Wang et al. Experimental demonstration and analysis of a 1.35-kV 0.92·mΩ∙cm2 SiC superjunction schottky diode. IEEE Trans Electron Devices, 65, 1458(2018).

    [40] S Harada, Y Kobayashi, S Kyogoku et al. First demonstration of dynamic characteristics for SiC superjunction MOSFET realized using multi-epitaxial growth method. International Electron Devices Meeting, 821(2018).

    [41] M Baba, T Tawara, T Morimoto et al. Ultra-low specific on-resistance achieved in 3.3 kV-class SiC superjunction MOSFET, 83(2021).

    [42] R Ghandi, C Hitchcock, S Kennerly et al. Demonstration of 3.5kV SiC deep-implanted superjunction didoes, 13(2023).

    [43] R Kosugi, S Ji, K Mochizuki et al. Breaking the theoretical limit of 6.5 kV-Class 4H-SiC super-junction (SJ) MOSFETs by trench-filling epitaxial growth, 39(2019).

    [44] J Knoll, M Shawky, S H Yen et al. Characterization of 4.5 kV charge-balanced SiC MOSFETs, 2217(2021).

    [45] R Ghandi, A Bolotnikov, D Lilienfeld et al. 3kV SiC charge-balanced diodes breaking unipolar limit, 179(2019).

    [46] R Ghandi, A Bolotnikov, S Kennerly et al. 4.5kV SiC charge-balanced MOSFETs with ultra-low on-resistance, 126(2020).

    [47] R Ghandi, C Hitchcock, S Kennerly et al. Scalable ultrahigh voltage SiC superjunction device technologies for power electronics applications, 911(2022).

    [48] T Masuda, Y Saito, T Kumazawa et al. 0.63 mΩ·cm2/1170 V 4H-SiC super junction V-groove trench MOSFET, 811(2018).

    [49] H Ishida, D Shibata, H Matsuo et al. GaN-based natural super junction diodes with multi-channel structures. IEEE International Electron Devices Meeting, 1(2018).

    [50] A Nakajima, Y Sumida, M H Dhyani et al. GaN-based super heterojunction field effect transistors using the polarization junction concept. IEEE Electron Device Lett, 32, 542(2011).

    [51] Z Li, T P Chow. Design and simulation of 5–20-kV GaN enhancement-mode vertical superjunction HEMT, 60, 3230(2013).

    [52] V Inni, L Hong, M SWEET et al. 2.4kV GaN polarization superjunction schottky barrier diodes on semi-insulating 6H-SiC substrate, 245(2014).

    [53] H Hahn, B Reuters, S Geipel et al. Charge balancing in GaN-based 2-D electron gas devices employing an additional 2-D hole gas and its influence on dynamic behaviour of GaN-based heterostructure field effect transistors. J Appl Phys, 117, 151(2015).

    [54] E Napoli. Superjunction. Wiley encyclopedia of electrical and electronics engineering. John Wiley: Sons, 1, 1(2014).

    [55] B Shankar, A Soni, S D Gupta et al. Safe operating area (SOA) reliability of polarization super junction (PSJ) GaN FETs. IEEE International Reliability Physics Symposium, 1(2018).

    [56] A Zhang, Z Qi, Y Chao et al. Novel AlGaN/GaN SBDs with nanoscale multi-channel for gradient 2DEG modulation, 204(2018).

    [57] S Han, J Song, M Sadek et al. 12.5 kV GaN super-heterojunction schottky barrier diodes. IEEE Trans Electron Devices, 68, 5736(2021).

    [58] Z Li, H Naik, T P Chow. Design of GaN and SiC 5–20kV vertical superjunction structures, 1(2012).

    [59] M Zhang, Z Guo, Y Huang et al. Study of AlGaN/GaN vertical superjunction HEMT for improvement of breakdown voltage and specific on-resistance. IEEE Access, 9895(2021).

    [60] M Xiao, Y Ma, Z Du et al. First demonstration of vertical superjunction diode in GaN, 35.6.1(2022).

    [61] Y Qin, M Porter, M Xiao et al. 2 kV, 0.7 mΩ·cm2 vertical Ga2O3 superjunction schottky rectifier with dynamic robustness, 1(2023).

    [62] B Zhang, W Zhang, J Zu et al. Novel homogenization field technology in lateral power devices. IEEE Electron Device Lett, 41, 1677(2020).

    [63] W T Zhang, Z J Li, B Zhang. A new type of homogenization field power semiconductor devices, 1(2022).

    [64] G Zhang, W Zhang, J He et al. Experiments of a novel low on-resistance LDMOS with 3-D floating vertical field plate, 507(2019).

    [65] W Zhang, Y Wu, K Zhang et al. Experiments of a lateral power device with complementary homogenization field structure. IEEE Electron Device Lett, 42, 1638(2021).

    [66] W Zhang, J He, Q Wu et al. A new multi-dimensional depletion concept of homogenization field devices. IEEE Electron Device Lett, 44, 1708(2023).

    [67] W Zhang, J Zu, X Zhu et al. Mechanism and experiments of a novel dielectric termination technology based on equal-potential principle, 38(2020).

    [68] X B Chen. Super-junction voltage sustaining layer with alternating semiconductor and high-K dielectric regions, 1, 1(2007).

    [69] X B Chen, M Huang. A vertical power MOSFET with an interdigitated drift region using high-K insulator. IEEE Trans Electron Devices, 59, 2430(2012).

    [70] X Lyu, X Chen. Vertical power high-K MOSFET of hexagonal layout. IEEE Trans Electron Devices, 60, 1709(2013).

    [71] X R Luo, J Y Cai, Y Fan et al. Novel low-resistance current path UMOS with high-K dielectric pillars. IEEE Trans Electron Devices, 60, 2840(2013).

    [72] W Chen, X B Cheng. A novel IGBT with high-K dielectric modulation achieving ultralow turn-off loss. IEEE Trans Electron Devices, 67, 1066(2020).

    [73] J Deng, J Cheng, X B Chen. An improved SOI p-channel LDMOS with high-K gate dielectric and dual hole-conductive paths. IEEE Electron Device Lett, 38, 1712(2017).

    [74] X Luo, M Lv, C Yin et al. Ultralow on-resistance SOI LDMOS with three separated gates and high-K dielectric. IEEE Trans Electron Devices, 63, 3804(2016).

    [75] Z Cao, B Duan, H Song et al. Novel superjunction LDMOS with a high-K dielectric trench by TCAD simulation study. IEEE Trans Electron Devices, 66, 2327(2019).

    [76] J Cheng, W Chen, J Lin et al. Potential of utilizing high-K film to improve the cost performance of trench LDMOS. IEEE Trans Electron Devices, 66, 3049(2019).

    [77] T Masuda, R Kosugi, T Hiyoshi. 0.97 mΩ·cm2/820 V 4H-SiC super junction V-groove trench MOSFET, 1(2016).

    [78] J Kemmerling, R Guan, M Sadek et al. GaN super-heterojunction FETs with 10-kV blocking and 3-kV dynamic switching. IEEE Trans Electron Devices, 71, 1153(2024).

    [79] Y Ma, M Poter, Y Qin et al. 1 kV self-aligned vertical GaN superjunction diode. IEEE Electron Device Lett, 45, 12(2024).

    [80] Y Qin, M Poter, M Xiao et al. 2 kV, 0.7 mΩ·cm2 vertical Ga2O3 superjunction schottky rectifier with dynamic robustness, 1(2023).

    [81] S Lee, K Oh, S Kim et al. 650V superjunction MOSFET using universal charge balance concept through drift region, 83(2014).

    [82] Y Wang, M Qiao, J Li et al. Optimization of reverse recovery characteristics based on termination structure for 700V super-junction VDMOS, 171(2023).

    [83] J Sakakibara, Y Noda, T Shibata et al. 600V-class super junction MOSFET with high aspect ratio P/N columns structure, 299(2008).

    [84] S Yamauchi, T Shibata, S Nogami et al. 200V super junction MOSFET fabricated by high aspect ratio trench filling, 1(2006).

    [85] Y Hattori, K Nakashima, M Kuwahara et al. Design of a 200V super junction MOSFET with n-buffer regions and its fabrication by trench filling, 189(2004).

    [86] T Nitta, T Minato, M Yano et al. Experimental results and simulation analysis of 250 V super trench power MOSFET (STM), 77(2000).

    Chao Ma, Weizhong Chen, Teng Liu, Wentong Zhang, Bo Zhang. Recent developments in superjunction power devices[J]. Journal of Semiconductors, 2024, 45(11): 111301
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