Design of a Four-Quadrant 14-bit Multiplying D/A Converter

LEI Langcheng; LUO Yanxin; LIU Honghong; DU Yubin; GAO Weiqi; ZHANG Jun; WU Qiuxia; FU Dongbing

doi:10.13911/j.cnki.1004-3365.220109

Journals >Microelectronics >Volume 52 >Issue 4 >Page 572 > Article

Microelectronics
Vol. 52, Issue 4, 572 (2022)

Design of a Four-Quadrant 14-bit Multiplying D/A Converter

LEI Langcheng, LUO Yanxin, LIU Honghong, DU Yubin, GAO Weiqi, ZHANG Jun, WU Qiuxia, and FU Dongbing

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[in Chinese]

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DOI: 10.13911/j.cnki.1004-3365.220109 Cite this Article

LEI Langcheng, LUO Yanxin, LIU Honghong, DU Yubin, GAO Weiqi, ZHANG Jun, WU Qiuxia, FU Dongbing. Design of a Four-Quadrant 14-bit Multiplying D/A Converter[J]. Microelectronics, 2022, 52(4): 572 Copy Citation Text

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References

[1] KESTER W. Data conversion handbook ［M］. Boston: Elsevier, 2004.

[2] MARCHE D, SAVARIA Y. Modeling R-2R segmented-ladder DACs ［J］. IEEE Trans Circ Syst, 2010, 57(1): 31-43.

[3] HOLLOWAY P, NORTON M. A high-yield second-generation 10-bit monolithic DAC ［C］// ISSCC. Philadelphia, PA, USA. 1976: 106-107.

LEI Langcheng, LUO Yanxin, LIU Honghong, DU Yubin, GAO Weiqi, ZHANG Jun, WU Qiuxia, FU Dongbing. Design of a Four-Quadrant 14-bit Multiplying D/A Converter[J]. Microelectronics, 2022, 52(4): 572

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