[5] LEE Y, SEONG T, YOO S, et al. A low-jitter and low-reference-spur ring-VCO-based switched-loop filter PLL using a fast phase-error correction technique ［J］. IEEE Journal of Solid-State Circuits, 2018, 53(4): 1192-1202.

[6] LOKE L S, BARNECE R K, WEE T, et al. A versatile low-jitter PLL in 90-nm CMOS transmitter clocking ［C］ // Proceedings of the IEEE 2005 Custom Integrated Circuits Conference. San Jose, CA, USA. 2005: 553-556.

[10] LEE I T, TSAI Y T, LIU S L. A leakage-current-recycling phase-locked loop in 65 nm CMOS technology ［C］ // IEEE Asian Sol Sta Circ Conf. Jeju, Korea. 2011: 2693-2700.