[1] HUNG J P,LIN J C,TSAI P H,et al. Interconnect structure for Package-on-Package devices:U.S., Patent,10/269,685[P]. 2019-4-23.
[2] HSU C L,LIU C S,LU D Y,et al. Package on package devices and methods of packaging semiconductor dies:U.S., Patent 8,981,559[P]. 2015-3-17.
[5] SU Y F,CHIANG K N,LIANG S Y. Design and reliability assessment of novel 3D-IC packaging[J]. Journal of Mechanics, 2017,33(2):193-203.