• Microelectronics
  • Vol. 52, Issue 4, 608 (2022)
ZHANG Haoran1, JIAO Zihao2, SHENG Wei1, ZHANG Yuxin1, CAO Yanjie1, and CHEN Minqi1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.220185 Cite this Article
    ZHANG Haoran, JIAO Zihao, SHENG Wei, ZHANG Yuxin, CAO Yanjie, CHEN Minqi. A 16-bit High-Precision Segmented-Resistance DAC[J]. Microelectronics, 2022, 52(4): 608 Copy Citation Text show less
    References

    [3] DEVEUGELE J, STEYAERT M S J. A 10-bit 250 MS/s binary-weighted current-steering DAC [J]. IEEE J Sol Sta Circ, 2006, 41(2): 320-329.

    [6] LEI W, FUKATSU Y, WATANABE K. A CMOS R-2R ladder digital-to-analog converter and its characterization [C]// IEEE IMTC. Budapest, Hungary. 2001: 1026-1031.

    [7] NOORWALI A A, DOOST A S, HUYNH A, et al. A 16-bit 4 MSPS DAC for lock-in amplifier in 65 nm CMOS [C]// IEEE 13th ICNSC. Mexico City, Mexico. 2016: 1-5.

    ZHANG Haoran, JIAO Zihao, SHENG Wei, ZHANG Yuxin, CAO Yanjie, CHEN Minqi. A 16-bit High-Precision Segmented-Resistance DAC[J]. Microelectronics, 2022, 52(4): 608
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