Qun-Gang Ma, Liu-Fei Zhou, Yue Yu, Guo-Yong Ma, Sheng-Dong Zhang. Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane [J]. Acta Physica Sinica, 2019, 68(10): 108501-1
- Acta Physica Sinica
- Vol. 68, Issue 10, 108501-1 (2019)
Fig. 1. Diagram of the GOA circuit unit composed of 13 TFTs and 1 capacitor.13T1C架构的GOA电路单元原理图
Fig. 2. ESD damage phenomenon of GOA circuit: (a) Photo image of the overall GOA where ESD damage occurs. (b) photo image of ESD damage M2 TFT in the GOA unit.GOA电路的ESD破坏现象 (a) GOA区大面积的ESD烧伤现象; (b) M2 TFT的ESD破坏现象
Fig. 3. Analysis of ESD failure area of M2 TFT: (a) FIB section analysis of ESD failure position; (b) elemental analysis of gate insulator at failure position of ESD.M2 TFT的ESD失效区域解析 (a) ESD失效位置的FIB断面解析; (b) ESD失效位置的栅极绝缘层元素分析
Fig. 4. M2 TFT characteristics at different positions from ESD failure center.距离ESD失效中心不同位置的M2 TFT特性
Fig. 5. Mechanism of space charge effect formed by Cu2+ ion entering SiO2.
Cu扩散引起的空间电荷效应与ESD失效机理
Fig. 6. Thickness contour distribution of Cu: SiNx /SiO2 three films.
Cu:SiNx /SiO2三层薄膜的厚度等值线分布
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Table 1. Comparison of different design schemes of M2 TFT in GOA.
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