• Chinese Journal of Quantum Electronics
  • Vol. 30, Issue 6, 743 (2013)
Yang DONG*, Min WU, Shan-qing GAO, and Hong-jun Lü
Author Affiliations
  • [in Chinese]
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    DOI: 10.3969/j.issn.1007-5461.2013.06.016 Cite this Article
    DONG Yang, WU Min, GAO Shan-qing, Lü Hong-jun. Design and optimization of quantum latch[J]. Chinese Journal of Quantum Electronics, 2013, 30(6): 743 Copy Citation Text show less
    References

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    [5] Wilde M M. Quantum-shift-register circuits [J]. Phys. Rev. A, 2009, 79(6): 062325.

    [7] Mozammel H A K. Design of reversible / quantum ternary multiplexer and demultiplexer [J]. Engin. Lett., 2006, 13(2): 65-69.

    [9] Thapliyal H, Srinivas M B, Zwolinski M. A beginning in the reversible logic synthesis of sequential circuits [C]. MAPLD International Conference, 2005, 10-12.

    [10] Thapliyal H, et al. Design of reversible latches optimized for quantum cost, delay and garbage outputs [C]. rd International Conference on VLSI Design, 2010, 235-240.

    [11] Maslov D. Efficient reversible and quantum implementations of symmetric Boolean functions [J]. IEEE Proc. Circuits Devices Syst., 2006, 153(5): 31-36.

    DONG Yang, WU Min, GAO Shan-qing, Lü Hong-jun. Design and optimization of quantum latch[J]. Chinese Journal of Quantum Electronics, 2013, 30(6): 743
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