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Journals >Journal of Semiconductors >Volume 44 >Issue 4 >Page 044102 > Article

Journal of Semiconductors
Vol. 44, Issue 4, 044102 (2023)

Temperature-insensitive reading of a flash memory cell

Weiyan Zhang^1、2, Tao Yu², Zhifeng Zhu¹, and Binghan Li^2、*

Author Affiliations

¹School of Information Science and Technology, ShanghaiTech University, Shanghai 201210, China

²Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai 200125, China

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DOI: 10.1088/1674-4926/44/4/044102 Cite this Article

Weiyan Zhang, Tao Yu, Zhifeng Zhu, Binghan Li. Temperature-insensitive reading of a flash memory cell[J]. Journal of Semiconductors, 2023, 44(4): 044102 Copy Citation Text

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References

[1] S T Han, Y Zhou, V A Roy. Towards the development of flexible non-volatile memories. Adv Mater, 25, 5425(2013).

[2] F Chen, B Chen, H Lin et al. Temperature impacts on endurance and read disturbs in charge-trap 3D NAND flash memories. Micromachines, 12, 1152(2021).

[3] D Resnati, A Goda, G Nicosia et al. Temperature effects in NAND flash memories: A comparison between 2-D and 3-D arrays. IEEE Electron Device Lett, 38, 461(2017).

[4] C Zambelli, G Koebernik, R Ullmann et al. Modeling erratic bits temperature dependence for Monte Carlo simulation of flash arrays. IEEE Electron Device Lett, 34, 390(2013).

[5] A Dilello, S Andryzcik, B M Kelly et al. Temperature compensation of floating-gate transistors in field-programmable analog arrays. 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1(2017).

[6] H Shin, M Oh, J Choi et al. A 28nm embedded flash memory with 100MHz read operation and 7.42Mb/mm2 at 0.85V featuring for automotive application. 2021 Symposium on VLSI Circuits, 1(2021).

[7] Q Dong, Z Wang, J Lim et al. A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. 2018 IEEE International Solid-State Circuits Conference (ISSCC), 480(2018).

[8] X Guo, F M Bayat, M Prezioso et al. Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells. 2017 IEEE Custom Integrated Circuits Conference (CICC), 1(2017).

[9] D H Jin, J W Kwon, M J Seo et al. A reference-free temperature-dependency-compensating readout scheme for phase-change memory using flash-ADC-configured sense amplifiers. IEEE J Solid-State Circuits, 54, 1812(2019).

[10] L Fang, W Kong, J Gu et al. A novel symmetrical split-gate structure for 2-bit per cell flash memory. J Semicond, 35, 074008(2014).

[11] H T Lue, T H Hsu, M T Wu et al. Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model. IEEE Trans Electron Devices, 53, 119(2006).

[13] A K Dwivedi, S Tyagi, A Islam. Threshold voltage extraction and its reliance on device parameters @ 16-nm process technology. Proceedings of the 2015 Third International Conference on Computer, Communication, Control and Information Technology (C3IT), 1(2015).

[14] C Tao, R A Vega, E Alptekin et al. Understanding short channel mobility degradation by accurate external resistance decomposition and intrinsic mobility extraction. J Appl Phys, 117, 64507(2015).

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Weiyan Zhang, Tao Yu, Zhifeng Zhu, Binghan Li. Temperature-insensitive reading of a flash memory cell[J]. Journal of Semiconductors, 2023, 44(4): 044102

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