A 40 V high-voltage output auto-zero operational amplifier was designed and implemented in a 0.6 μm BCD process. A time-interlaced auto-zero structure was utilized to achieve continuous calibration of the input offset voltage. A high-voltage class AB stage based on 40 V PDMOS and NDMOS transistors was utilized at the output stage. The input stage and auto-zero calibration circuit of the operational amplifier were based on 0.6 μm standard MOS transistor which operated on a single 5 V power supply. The middle amplification stage and output stage utilized 40 V DMOS with asymmetric structure to realize high-voltage output. In the overall circuit, only the drain-source voltage of DMOS transistors withstood a voltage of 40 V, and the voltage under the other MOS transistors was within the proper power supply range, so there was no voltage to withstand exceeding risk. The pre-simulation results show that the operational amplifier operates under 5 V and 40 V dual power supply, and the input offset voltage is 0.78 μV. The output voltage range is 3.0-37.7 V. The equivalent DC gain is 142.7 dB. The unit gain bandwidth is 1.9 MHz. The common mode rejection ratio is 154.8 dB. The 40 V power supply rejection ratio is 152.3 dB, and the 5 V power supply rejection ratio is 134.9 dB.