A high frequency ultra-wideband digital step attenuator with low insertion loss and large attenuation range was designed and implemented in a 65 nm CMOS process. Bridged-T and π-type switch embedded attenuation structure was adopted for good port matching performance and high attenuation accuracy. Constant negative voltage bias was adopted to reduce insertion loss and improve ultra-wideband performance. Cascade design of attenuation cells with high matching was adopted to realize high attenuation accuracy under large attenuation range. The measured results show that the maximum attenuation value is 31.5 dB, the attenuation step is 0.5 dB, the insertion loss of reference state is less than 3.5 dB, and the rms of amplitude error is less than 0.45 dB at 10 MHz~30 GHz. The total chip size is 2.30×1.20 mm2.