A high-speed data acquisition system using CPLD as an acquisition control unit is designed. CPLD is used to control the time sequence of serial AD and serial ferroelectric memory in the system. And CPLD is helpful to perform logic control and time sequence coordination on single chip C8051F020. The system has the characteristics of 2 MHZ sampling frequency, 12-bits sampling precision, small volume and low power dissipation. The design is applied in experimental test successfully and its performance and indexes are both better than application requirements.