• Microelectronics
  • Vol. 51, Issue 4, 603 (2021)
QIAN Lingli and HUANG Wei
Author Affiliations
  • [in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.200472 Cite this Article
    QIAN Lingli, HUANG Wei. ESD Failure Analysis and Improvement of a Special Digital Circuit for Multi-Power Supply Domain[J]. Microelectronics, 2021, 51(4): 603 Copy Citation Text show less
    References

    [1] LIU J Z, QIAN L L, RUI T, et al. Self-triggered stacked silicon-controlled rectifier structure (STSSCR) for on-chip electrostatic discharge (ESD) protection [J]. Microelec Reliab, 2017, 71(4): 1-5.

    [2] KER M D, LIN C Y. High-voltage-tolerant ESD clamp circuit with low standby leakage in nanoscale CMOS process [J]. IEEE Trans Elec Dev, 2010, 57(7): 1636-1641

    [3] SHRIVASTAVA M, GOSSNER H. A review on the ESD robustness of drain extended MOS devices [J]. IEEE Trans Dev & Mater Reliabil, 2012, 12(4): 615-625.

    [4] LEE J HG, IYER N M, PRABHU M, et al. ESD robust fully salicided 5-V integrated power MOSFET in submicron CMOS [J]. IEEE Elec Dev Lett, 2017, 38(5): 623-625.

    [5] KHAZHINSKY M G, MILLER J W, STOCKINGER M, et al. Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies [C] // Electrical Overstress / Electrostatic Discharge Symp. Grapevine, TX, USA. 2004: 255-264.

    [6] POON S, MALONEY T. New considerations for MOSFET power clamps [C] // Electrical Overstress/ Electrostatic Discharge Symp. Charlotte, NC, USA. 2002: 1-5.

    [7] SMITH J, BOSELLI G. A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies [C] // Electrical Overstress / Electrostatic Discharge Symp. Las Vegas, NV, USA. 2003: 8-16.

    [8] TORRES C A, MILLER J W, STOCKINGER M, et al. Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies [C] // Electrical Overstress / Electrostatic Discharge Symp. Portland, OR, USA. 2001: 82-95.

    [9] KER M D, CHANG W J. ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers [J]. IEEE Trans Elec Dev, 2008, 55(6): 1409-1416.

    [10] XIN W, SHI Z T, LIU J, et al. Post-Si programmable ESD protection circuit design: mechanisms and analysis [J]. IEEE J Sol Sta Circ, 2013, 48(5): 1237-1249.

    QIAN Lingli, HUANG Wei. ESD Failure Analysis and Improvement of a Special Digital Circuit for Multi-Power Supply Domain[J]. Microelectronics, 2021, 51(4): 603
    Download Citation