The remote sensing equipment needs to be equipped with a high precision local clock source in order to synchronize with the clock of the satellite platform. The digital phase locked-loop design is a key technology of synchronization and frequency multiplication of the clock. Long period input signals and large frequency multiplication coefficient add more difficulties of the loop design from two different ways. Under the condition of second pulse synchronization and 10000 times frequency multiplication, a method of digital loop parameter algorithm was proposed. The response characteristics of the loop were analyzed by establishing the Z domain model and the approximate S domain model. The whole design was implemented by field programmable gate array. Experiments show that the design of the digital phase-locked loop can be locked in 5 input clock cycles, and the cumulative error is less than 0.1 ms per second during stable operation. In practical application, the digital phase locked loop can stabilize the output of the local clock to meet the needs of the remote sensing devices’ clock synchronization and frequency multiplication.