Author Affiliations
1State Key Laboratory of Precision Measuring Technology and Instruments, Tianjin University, Tianjin 300072, China2MOEMS Education Ministry Key Laboratory, Tianjin University, Tianjin 300072, Chinashow less
Fig. 1. Schematic diagram of SMAD method
Fig. 2. Multistage pipelined adder
Fig. 3. Comparison before and after optimization of SMAD method
Fig. 4. Pyramid-like strategy
Fig. 5. Structural diagram of the target tracking platform
Fig. 6. Hardware architecture for maximum and minimum filtering
Fig. 7. Flowchart of the target search module
Fig. 8. Comparison of tracking indicators between SMAD and SAD
Fig. 9. Scale switching of the template
Fig. 10. Performance comparison of each template matching algorithm tracking the car sequence
Fig. 11. Functional simulation waveform of the target tracking module
Fig. 12. Tracking experiment for a target tracking system
Fig. 13. Anti-occlusion test of target tracking system
Metrics | Foreign FPGA | Domestic FPGA | Types | More | Fewer | Process | 7 nm | 28 nm | Gates | 100 million | Most: 10 million | IP cores | More | Fewer | Market | High/mid/low end | Mid/low end | Technology | Mature | Immature | Autonomy | Poor | Better |
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Table 1. Comparison of domestic and foreign FPGAs
| Rotational deformation | | Scale change | | Partial occlusion | | Various scenarios | | Success rate | AOR | Success rate | AOR | Success rate | AOR | Success rate | AOR | SAD | 0.7604 | 0.39548 | | 0.8012 | 0.5364 | | 0.7412 | 0.33176 | | 0.7680 | 0.3818 | SSD | 0.7563 | 0.36219 | 0.7786 | 0.4997 | 0.7454 | 0.33879 | 0.7511 | 0.3695 | NCC | 0.7588 | 0.39248 | 0.7567 | 0.4404 | 0.7362 | 0.30951 | 0.7467 | 0.4228 | BSS | 0.7642 | 0.45265 | 0.8385 | 0.6817 | 0.784 7 | 0.50696 | 0.7851 | 0.4974 | DDIS | 0.768 3 | 0.456 25 | 0.8273 | 0.6188 | 0.7802 | 0.509 51 | 0.8197 | 0.5399 | SMAD-0 | 0.7640 | 0.44162 | 0.8261 | 0.5583 | 0.7775 | 0.48105 | 0.7842 | 0.4974 | SMAD | 0.7634 | 0.44186 | 0.859 4 | 0.682 1 | 0.7791 | 0.48060 | 0.829 4 | 0.540 6 |
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Table 2. Comparison of metrics for each tracking algorithm
Resources | Consumption | Consumption percentage | LUTs | 48457 | 72.76% | Registers | 58587 | 43.98% | DRM | 36.5 | 23.55% | I/O ports | 102 | 34.00% |
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Table 3. Resource consumption of the FPGA