The successive approximation analog-to-digital converter (SAR ADC) has become the preferred architecture of ADC in low power digital-analog hybrid integrated circuit. As the core module, the power of high performance comparator directly determines the overall power dissipation of SAR ADC. Starting from the low power SAR ADC system, this work focused on the development histories and latest research progresses of high performance low power voltage and time domain comparators, and summarized the techniques of realizing low power comparator by optimizing SAR logic. This work could help mixed-signal circuit designers understand the new techniques of low power comparator in SAR ADC.