• Microelectronics
  • Vol. 52, Issue 3, 426 (2022)
SHENG Yongxia1, LIANG Huaguo1, XIAO Yuan1, JIANG Cuiyun2, YI Maoxiang1, and LU Yingchun1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.210385 Cite this Article
    SHENG Yongxia, LIANG Huaguo, XIAO Yuan, JIANG Cuiyun, YI Maoxiang, LU Yingchun. An Approximate Booth Multiplier Based on Novel Wallace Tree[J]. Microelectronics, 2022, 52(3): 426 Copy Citation Text show less
    References

    [1] ALIOTO M. Ultra-low a power VLSI circuit design demystified and explained: A tutorial [J]. IEEE Trans Circ Syst I: Regu Pap, 2012, 59(1): 3-29.

    [2] HAN J, ORSHANSKY M. Approximate computing: an emerging paradigm for energy-efficient design [C]// 18th IEEE ETS. Avignon, France. 2013: 1-6.

    [3] LIU W, LOMBARDI F, SHULTE M. A retrospective and prospective view of approximate computing [J]. Proceed IEEE, 2020, 108(3): 394-399.

    [4] JIANG H, SANTIAGO F J H, MO H, et al. Approximate arithmetic circuits: a survey, characterization, and recent applications [J]. Proceed IEEE, 2020, 108(12): 2108-2135.

    [5] LIUW, CAO T, YIN P, et al. Design and analysis of approximate redundant binary multipliers [J]. IEEE Trans Comput, 2018, 68(6): 804-819.

    [6] MITCHELL J N. Computer multiplication and division using binary logarithms [J]. IRE Trans Elec Comput, 1962 (4): 512-517.

    [7] CUI X, LIU W, CHEN X, et al. A modified partial product generator for redundant binary multipliers [J]. IEEE Trans Comput, 2015, 65(4): 1165-1171.

    [8] LIU W, QIAN L, WANG C, et al. Design of approximate radix-4 booth multipliers for error-tolerant computing [J]. IEEE Trans Comput, 2017, 66(8): 1435-1441.

    [9] JIANG H, HAN J, QIAO F, et al. Approximate radix-8 booth multipliers for low-power and high-performance operation [J]. IEEE Trans Comput, 2015, 65(8): 2638-2644.

    [10] LEON V, ZERVAKIS G, SOUDRIS D, et al. Approximate hybrid high radix encoding for energy-efficient inexact multipliers [J]. IEEE Trans VLSI Syst, 2017, 26(3): 421-430.

    [11] CHO K J, LEE K C, CHUNG J G, et al. Design of low-error fixed-width modified booth multiplier [J]. IEEE Trans VLSI Syst, 2004, 12(5): 522-531.

    [12] CHEN K, LIU W, HAN J, et al. Profile-based output error compensation for approximate arithmetic circuits [J]. IEEE Trans Circ Syst I: Regu Pap, 2020, 67(12): 4707-4718.

    [13] FRUSTACI F, PERRI S, CORSONELLO P, et al. Approximate multipliers with dynamic truncation for energy reduction via graceful quality degradation [J]. IEEE Trans Circ Syst II: Expr Bri, 2020, 67(12): 3427-3431.

    [14] VENKATACHALAM S, LEE H J, KO S B. Power efficient approximate booth multiplier [C]// IEEE ISCAS. Florence, Italy. 2018: 1-4.

    [15] MAHESHWARI N, YANG Z, HAN J, et al. A design approach for compressor based approximate multipliers [C]// 28th Int Conf VLSI Design. Bangalore, India. 2015: 209-214.

    [16] SABETZADEH F, MOAIYERI M H, AHMADINEJAD M. A majority-based imprecise multiplier for ultra-efficient approximate image multiplication [J]. IEEE Trans Circ Syst I: Regu Pap, 2019, 66(11): 4200-4208.

    [17] BOOTH A D. A signed binary multiplication technique [J]. The Quarterly J Mechanics Appl Math, 1951, 4(2): 236-240.

    [18] MACSORLEYO L. High-speed arithmetic in binary computers [J]. Proceed IRE, 1961, 49(1): 67-91.

    [19] MOMENI A, HAN J, MONTUSCHI P, et al. Design and analysis of approximate compressors for multiplication [J]. IEEE Trans Comput, 2014, 64(4): 984-994.

    [21] QIAN L, WANG C, LIU W, et al. Design and evaluation of an approximate Wallace-Booth multiplier [C]// IEEE ISCAS. Mantreal, Canada. 2016: 1974-1977.

    [22] WANG Z, BOVIK A C, SHEIKH H R, et al. Image quality assessment: from error visibility to structural similarity [J]. IEEE Trans Image Process, 2004, 13(4): 600-612.

    SHENG Yongxia, LIANG Huaguo, XIAO Yuan, JIANG Cuiyun, YI Maoxiang, LU Yingchun. An Approximate Booth Multiplier Based on Novel Wallace Tree[J]. Microelectronics, 2022, 52(3): 426
    Download Citation