[2] YOOK J M, SIM S H, PARK B J, et al. Integrated circuit (IC)-embedded wafer-level packaging technology for millimeter-wave power ICs ［J］. Microw Optical Technol Lett, 2019, 61(9): 2210-2213.
[3] CHANG Y J, HSIEH Y S, CHEN K N. Submicron Cu/Sn bonding technology with transient Ni diffusion buffer layer for 3D IC application ［J］. IEEE Elec Dev Lett, 2014, 35(11): 22-24.
[4] KHAN W T, LOPEZ A V, ULUSOY A C, et al. Packaging a W-band integrated module with an optimized flip-chip interconnect on an organic substrate ［J］. IEEE Trans Microw Theo Tech, 2014, 62(1): 64-72.
[5] FAKHARZODEL M, TAZLAUANU M. Methods for failure analysis and diagnosis of millimeter-wave system-in-packages ［J］. IEEE Trans Dev Mater Reliab, 2017, 17(2): 371-380.
[7] LEE C C, HUANG P C, LIAN Y C, et al. Demonstration of an equivalent material approach for the strain-induced reliability estimation of stacked-chip packaging［J］.IEEE Trans Dev Mater Reliab, 2020, 20(2): 475-482.
[8] MAKHLOUF S, STEEG M, HADDAD T, et al. Novel 3-D multilayer terahertz packaging technology for integrating photodiodes arrays and rectangular waveguide-power combiners ［J］. IEEE Microw Theo Tech, 2020, 68(1): 4611-4619.
[9] CHAN J M, LEE K C, TAN C S. Effects of copper migration on the reliability of through-silicon via (TSV) ［J］. IEEE Trans Dev Mater Reliab, 2018, 18(4): 520-528.
[10] ZHANG X F, WANG Y W, IM J H, et al. Chip-package interaction and reliability improvement by structure optimization for ultralow-k interconnects in flip-chip packages ［J］. IEEE Trans Dev Mater Reliab, 2012, 12(2): 462-469.
[11] HU S, HOE Y Y G, LI H G, et al. A thermal isolation technique using through-silicon for three-dimensional ICs ［J］. IEEE Trans Elec Dev, 2013, 60(3): 1282-1286.
[12] JIANG D, MU W, CHEN S, et al. Vertically stacked carbon nanotube-based interconnects for through silicon via application ［J］. IEEE Elec Dev Lett, 2015, 36(5): 499-503.
[13] CRATON M T, KENSTANTUNOU X F, ALBRECHT J D. Additive manufacturing of a W-band system-on-package ［J］. IEEE Trans Microw Theo Techni, 2021, 69(9): 4191-4198.
[14] WEI P S, TSAI M H, HSU S K, et al. An electromagnetic bandgap structure integrated with RF LNA using integrated fan-out wafer-level package for gigahertz noise suppression ［J］. IEEE Trans Microw Theo Tech, 2018, 66(12): 5482-5490.
[15] LEE K W, WANG H, BEA J C, et al. Barrier properties of Mn CVD oxide layer to Cu diffusion for 3D TSV ［J］. IEEE Elec Dev Lett, 2014, 35(1): 114-116.
[16] CASSIDY C, KRAFT J, COMIELLO S, et al. Through silicon via reliability ［J］. IEEE Trans Dev Mater Reliab, 2012, 12(2): 285-295.
[17] LU Y, YU D, WAN L X, et al. The redistribution layer-first embedded fan-out wafer level packaging for 2-D ultrasonic transducer arrays ［J］. IEEE Elec Dev Lett, 2021, 42(9): 1374-1377.
[18] KIM S M, LEE K C,YU Y M, et al. Wafer-level packaged light-emitting diodes using photodielectric resin ［J］. IEEE Trans Dev Lett, 2009, 30(6): 638-640.
[19] ZHANG J, BLOOMFIELD M O, LU J Y, et al. Modeling thermal stress in 3-D IC interwafer interconnects ［J］. IEEE Trans Semicond Manuf, 2006, 19(4): 437-448.
[20] COTTERELL B, CHEN Z, HAN J B, et al. The strength of the silicon die in flip-chip assemblies ［J］. ASME Trans J Elec Packag, 2003, 125(1): 114-119.
[21] CASSIDY C, TEVA J, KRAFT J, et al, Through silicon via (TSV) defect investigations using lateral emission microscopy ［J］. Microelec Reliab, 2010, 50(9-11): 1413- 1416.
[22] MARCHAL P, BOUGARD B, KATTI G, et al. 3-D technology assessment path - finding the technology/design sweet-spot ［J］. Proceed IEEE, 2009, 97(1): 96-107.
[27] LIU F, MENG G. Random vibration reliability of BGA lead-free solder joint ［J］. Microelec Reliab, 2014, 54(1): 226-232.
[28] KIM Y K, HWANG D S. PBGA packaging reliability assessments under random vibrations for space applications ［J］. Microelec Reliab, 2015, 55(1): 172-179.
[29] LIU B L, TIAN Y H, QIN J K, et al. Degration behaviors of micro ball grid array (μBGA) solder joints under the coupled effects of electromigration and thermal stress ［J］. J Mater Sci: Mater Elec, 2016, 27(11): 11583-11592.
[30] MIRMAN B. Tools for stress analysis of microelectronic structures ［J］. J Elec Packag, 2000, 122(3): 280-282.
