• Microelectronics
  • Vol. 53, Issue 5, 747 (2023)
XIE Hanjun1、2, WANG Yan2、3, and FU Xiaojun2、3
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • 3[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.230003 Cite this Article
    XIE Hanjun, WANG Yan, FU Xiaojun. A Third-Order Hybrid Structure Noise-Shaping SAR ADC[J]. Microelectronics, 2023, 53(5): 747 Copy Citation Text show less
    References

    [3] FREDENBURG J, FLYNN M. A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC [C]// IEEE International Solid-State Circuits Conference. San Francisco, CA, USA. 2012: 468-470.

    [4] CHEN Z, MIYAHARA M, MATSUZAWA A. A 9.35-ENOB, 14.8-fJ/conv.-step fully-passive noise-shaping SAR ADC [C]// Symposium on VLSI Circuits. Kyoto, Japan. 2015: C64-C65.

    [5] GUO W, ZHUANG H, SUN N. A 13 b-ENOB 173 dB-FoM 2nd-order NS SAR ADC with passive integrators [C]. Symposium on VLSI Circuits. Kyoto, Japan. 2017: C236-C237.

    [6] LI S, QIAO B, GANDARA M, et al. A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure [J]. IEEE Journal of Solid-State Circuits, 2018, 53(12): 3484-3496.

    [7] GUO W, SUN N. A 12 b-ENOB 61 μW noise-shaping SAR ADC with a passive integrator [C]// Eur Solid-State Circuits Conf. Lausanne, Switzerland. 2016: 405-408.

    [8] ZHANG Q, NING N, ZHANG Z, et al. A 13-bit third-order noise-shaping SAR ADC employing hybird error control structure and LMS-based foreground digital calibration [J]. IEEE Journal of Solid-State Circuits, 2022, 57(7): 2181-2195.

    [10] ZHU Y, CHAN C, ZHAO U, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2010, 45(6): 1111-1121.