A Dual Loop Adaptive CTLE with Spectrum Balancing

WU Hao; ZHAN Yinhang

doi:10.13911/j.cnki.1004-3365.210128

[1] ZHANG F, ZHU Y, YANG F, et al. Up to single lane 200G optical interconnects with silicon photonic modulator ［C］ // IEEE OFC. San Diego, CA, USA. 2019: 1-3.

[3] LI S B, JIANG Y T, LIU P. An adaptive PAM-4 analog equalizer with boosting-state detection in the time domain ［J］. IEEE Trans VLSI Syst, 2017, 25(10): 2907-2916.

[4] LEE J. A 20-Gb/s adaptive equalizer in 013-μm CMOS technology ［J］. IEEE J Sol Sta Circ, 2006, 41(9): 2058- 2066.

[5] CAI C, ZHOU Y M, ZHAO J Z. 5-20 Gbit/s adaptive CTLE with spectrum balancing method ［J］. Elec Lett, 2018, 54(5): 274-276.

[6] LI J Q, CHEN Y M, CHEN L F, et al. A 30 Gbps power-efficient dual-loop adaptive equalizer in 013 μm SiGe BiCMOS technology ［J］. Microelec J, 2020, 100: 104773

[7] LIM B, YOO C. A 12-Gb/s continuous-time linear equalizer with offset canceller ［J］. J Semicond Technol & Sci, 2019, 19(2): 220-225.

[8] TALLURI G R, BAGHINI M S. A novel dual loop adaptive equalizer based on spectrum balancing technique ［J］. Microelec J, 2019, 87: 127-135.

[9] TALLURI G R, RAKESH K K, BAGHINI M S. A 4-14 Gbps inductor-less adaptive linear equalizer using hybrid filter in 65 nm CMOS technology ［C］ // 16th Int Symp Qual Elec Des. Santa Clara, CA, USA. 2015: 90-97.

[10] TALLURI G R, SHOJAEI B M. A closed loop inductorless equalizer with a modified analysis of power comparator behaviour ［J］. Int J Circ Theo & Appl, 2020, 48(5): 777-788.