Implementation of 2D DCT based on FPGA

[in Chinese]; [in Chinese]

Journals >Infrared and Laser Engineering >Volume 32 >Issue 4 >Page 436 > Article

Infrared and Laser Engineering
Vol. 32, Issue 4, 436 (2003)

Implementation of 2D DCT based on FPGA

[in Chinese]^* and [in Chinese]

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[in Chinese]

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[in Chinese], [in Chinese]. Implementation of 2D DCT based on FPGA[J]. Infrared and Laser Engineering, 2003, 32(4): 436 Copy Citation Text

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References

[1] Ahmed N, Natarajan T, Rao K R. Discrete cosine transform[J]. IEEE Trans Comput, 1974,C-23: 90-93.

[2] ISO/IEC 13818-2. Information technology-generic coding of moving pictures and associated audio information: video[S]. 1995.

[3] Thou-ho Chen. A cost-effective 8×8 2-D IDCT core processor with folded architecture[J]. IEEE Trans on Consumer Electronics, 1999,45(2):333-339.

[4] Nam Ik Cho, Sang Uk Lee. Fast algorithm and implementation of 2-D discrete cosine transformation[J]. IEEE Trans on Circuits and Systems, 1991,38( 3):297-305.

[5] Lee Y P, Chen T H, Chen L G. A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method[J]. IEEE Trans on Circuits and System for Video Technology, 1997,7( 3 ):459-467.

[6] White S A. Applications of distributed arithmetic to digital signal processing[J]. IEEE ASSP Magazine, 1989, 6(3):4-19.

[in Chinese], [in Chinese]. Implementation of 2D DCT based on FPGA[J]. Infrared and Laser Engineering, 2003, 32(4): 436

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