• Microelectronics
  • Vol. 52, Issue 3, 418 (2022)
WANG Jian1, CHEN Hongmei1、2, ZHANG Haozhe1, WANG Lanyu1, and YIN Yongsheng1、2
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.210364 Cite this Article
    WANG Jian, CHEN Hongmei, ZHANG Haozhe, WANG Lanyu, YIN Yongsheng. Design of a Digital Down Converter in High Speed TIADC Acquisition System[J]. Microelectronics, 2022, 52(3): 418 Copy Citation Text show less
    References

    [1] LIU T, HAN J, LI Z. Broadband DDC based on polyphase filter and its FPGA implementation [C]// IEEE ICEICT. Harbin, China. 2016: 170-173.

    [2] KOVAR P, PURICER P, MORONG T, et al. Digital up and down converter for high performance VHF and UHF transceiver [C]// Int Conf Appl Elec. Pilsen, Czech Republic. 2019: 1-4.

    [3] DALVI P, PATIL P, VERMA D, et al. Field programmable gate array based implementation of digital down converter for magnetic resonance imaging [C]// 4th ICCUBEA. Pune, India. 2018: 1-4.

    [4] ZHUO Z H, LI S G, LI W G, et al. Implementation of high-performance multi-structure digital down converter based on FPGA [C]// IEEE 11th Int Conf Signal Process. Beijing, China. 2012: 31-35.

    [5] DATTA D, MITRA P, DUTTA H S. FPGA-based digital down converter for GSM application [C]// IEEE VLSI DCS. Kolkata, India. 2020: 299.

    [6] PAVLENKO M, KALYUZHNY A. Analysis of quantization noises in multistage signal processing systems: a case study of digital down converters (DDC) [C]// IEEE First UKRCON. Kyiv, Ukraine. 2017: 822-825.

    [7] MAITI G, SHANKAR B R, KUMAR T N, et al. Variable fractional rate digital down converter for satellite communication [C]// IEEE 9th LATINCOM. Guatemala City, Guatemala. 2017: 1-6.

    [10] YIN Y S, WAN Z J, CHEN H M, et al. Background timing mismatch calibration technique for TIADC in Nyquist frequency band [J]. Elec Lett, 2020, 56(15): 753-756.

    [11] LEI Z, WANG W. The design of NCO based on CORDIC algorithm and implementation in FPGA [C]// ICECC. Ningbo, China. 2011: 2902-2905.

    [13] CHANG Y J, CHENG Y C, LIAO S C, et al. A low power Radix-4 booth multiplier with pre-encoded mechanism [J]. IEEE Access, 2020, 8(5): 114842-114853.

    [14] ASIF S, KONG Y. Performance analysis of wallace and radix-4 booth-wallace multipliers [C]// Elec Syst Level Synth Conf. San Francisco, CA, USA. 2015: 17-22.

    [15] RAHNAMAEI A, FATIN G Z. High speed 16×16 bit booth multiplier based on novel 4-2 compressor structure [C]// 1st Int Conf ARES. Dubai, United Arab Emirates. 2018: 1-5.

    [16] SHARMA I, KUMAR A, SINGH G K, et al. Design of multiplier less prototype filter for two-channel filter bank using hybrid method in FCSD space [J]. IET Circ Dev & Syst, 2016: 11(1): 29-40.

    [18] AN J, CHO J, PARK D. On-chip glitch-free backup clock changer with noise canceller and edge detector for safety MCU clock system [C]// IEEE 4th GCCE. Osaka, Japan. 2015: 487-488.

    WANG Jian, CHEN Hongmei, ZHANG Haozhe, WANG Lanyu, YIN Yongsheng. Design of a Digital Down Converter in High Speed TIADC Acquisition System[J]. Microelectronics, 2022, 52(3): 418
    Download Citation