• Microelectronics
  • Vol. 52, Issue 2, 206 (2022)
ZENG Tao, GUO Liang, HOU Jiang, LIAO Wang, CHEN Xue, WANG Guoqiang, and HUANG Xiaozong
Author Affiliations
  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.zjea001 Cite this Article
    ZENG Tao, GUO Liang, HOU Jiang, LIAO Wang, CHEN Xue, WANG Guoqiang, HUANG Xiaozong. A High Speed ADC Using Low Threshold Technology[J]. Microelectronics, 2022, 52(2): 206 Copy Citation Text show less
    References

    [1] LEE S, CHANDRAKASAN A P, LEE H S. A 1 GS/s 10 b 189 mW time-interleaved SAR ADC with background timing-skew calibration [C]// IEEE ISSCC. San Francisco, CA, USA. 2014: 384-385.

    [2] KULL L, LUU D, MENOLFI C, et al. A 24-72-GS/s 8-b time-interleaved SAR ADC with 20-33-pJ/conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET [C]// IEEE ISSCC. San Francisco, CA, USA. 2018: 358-360.

    [3] ALI A M A, DINC H, BHORASKAR P, et al. A 14-bit 25 GS/s and 5 GS/s RF sampling ADC with background calibration and dither [C]// VLSI-Circ. Honolulu, HI, USA. 2016: 1-2.

    [4] DEVARAJAN S, SINGER L, KELLY D, et al. A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology [J]. IEEE J Sol Sta Circ, 2017, 52(12): 3204-3218.

    [5] ALI A M A, DINC H, BHORASKAR P, et al. A 12 b 18 GS/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration [C]// IEEE ISSCC. San Francisco, CA, USA. 2020: 250-251.

    [6] ZHANG M L, ZHU Y, CHAN C H, et al. A 4×interleaved 10 GS/s 8 b time-domain ADC with 16×interpolation-based inter-stage gain achieving >375 dB SNDR at 18 GHz input [C]// IEEE ISSCC. San Francisco, CA, USA. 2020: 252-253.

    [7] TAFT R C, FRANCESE P A, TURSI M R, et al. A 18 V 10 GS/s 10 b self-calibrating unified-folding-interpolating ADC with 91 ENOB at Nyquist frequency [J]. IEEE J Sol Sta Circ, 2009, 44(12): 3294-3304.

    [8] NAKAJIMA Y, SAKAGUCHI A, OHKIDO T, et al. A background self-calibrated 6 b 27 GS/s ADC with cascade - calibrated folding - interpolating architecture [J]. IEEE J Sol Sta Circ, 2010, 45(4): 707-718.

    [9] RITTER P, LE TUAL S, ALLARD B, et al. Design considerations for a 6 bit 20 GS/s SiGe BiCMOS flash ADC without track-and-hold [J]. IEEE J Sol Sta Circ, 2014, 49(9): 1886-1894.

    [10] ZANDIEH A, SCHVAN P, VOINIGESCU S P. Design of a 55-nm SiGe BiCMOS 5-bit time-interleaved flash ADC for 64-Gbd 16-QAM fiberoptics applications [J]. IEEE J Sol Sta Circ, 2019, 54(9): 2375-2387.

    [12] LUO L, LIN K H, CHENG L, et al. A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend [C]// ESSCIRC. Athens, Greece. 2009: 472-475.

    [13] LEE B, MIN B, MANGANARO G, et al. A 14 b 100 MS/s pipelined ADC with a merged active S/H and first MDAC [C]// IEEE Int Sol Sta Circ Conf. San Francisco, CA, USA. 2008: 248-249, 611.

    ZENG Tao, GUO Liang, HOU Jiang, LIAO Wang, CHEN Xue, WANG Guoqiang, HUANG Xiaozong. A High Speed ADC Using Low Threshold Technology[J]. Microelectronics, 2022, 52(2): 206
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