• Electronics Optics & Control
  • Vol. 23, Issue 8, 85 (2016)
CHEN Zhan-liang1、2, JIN Long-xu1, TAO Hong-jiang1, and HAN Shuang-li1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.3969/j.issn.1671-637x.2016.08.020 Cite this Article
    CHEN Zhan-liang, JIN Long-xu, TAO Hong-jiang, HAN Shuang-li. Implementation of DDR3 Controller in High-Speed Image Compression System[J]. Electronics Optics & Control, 2016, 23(8): 85 Copy Citation Text show less

    Abstract

    Digital remote sensing images have the features of real-time processing and huge amount of data. To meet the needs of high-capacity and high bandwidth in image processing system, DDR3 controller in spartan6 FPGA is used to realize reading/writing operation to DDR3 memory, which converts the complicated timing operation into a simple user interface. The features of DDR3 memory and the principle of DDR3 controller are introduced, and the hardware test to the DDR3 controller shows that it can work steadily. The controller is used successfully in the real-time image compression system by parameter configuration and interface design. With high-capacity and high bandwidth, DDR3 memory has found a wide application.
    CHEN Zhan-liang, JIN Long-xu, TAO Hong-jiang, HAN Shuang-li. Implementation of DDR3 Controller in High-Speed Image Compression System[J]. Electronics Optics & Control, 2016, 23(8): 85
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