Author Affiliations
1School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, Zhejiang 310018, China2Key Laboratory of Space Laser Communication and Detection Technology, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China3Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, Chinashow less
Fig. 1. Schematic of Φ-OTDR experimental system
Fig. 2. Format of data frame
Fig. 3. Signal processing steps of Φ-OTDR system
Fig. 4. Schematic of FPGA implementation
Fig. 5. Pipeline using in system. (a) Structure of pipeline; (b) timing of FFT pipeline process
Fig. 6. Sliding read and combination of data frame
Fig. 7. Process of FFT calculation
Fig. 8. Process of filtering calculation
Fig. 9. Accuracy of FFT calculation
Fig. 10. Actual calculation results. (a) FPGA FFT;(b) MATLAB FFT
Fig. 11. Transition display of disturbance
Fig. 12. Disturbance andmagnified image of disturbance point
Fig. 13. Frequency spectrum analysis. (a) Frequency spectrum without disturbance point; (b) frequency spectrum with disturbance point
Fig. 14. Results of filtering. (a) Result before filtering; (b) result after filtering
Resource | Usage | Availability | Utilization /% |
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LUT | 39177 | 133800 | 29.28 | LUTRAM | 9079 | 46200 | 19.65 | FF | 60621 | 267600 | 22.65 | BRAM | 250.50 | 365 | 68.63 | DSP | 450 | 740 | 60.81 | IO | 153 | 400 | 38.25 | MMCM | 3 | 10 | 30 | PLL | 1 | 10 | 10 | PCIe | 1 | 1 | 100 |
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Table 1. Resource utilization of FPGA
Environment | Specification | FFT number |
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10,000 | 20,000 | 30,000 | 40,000 | 50,000 |
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FPGA Atrix-7 | 200 MHz, 1 core | 25.8 ms | 51.7 ms | 77.6 ms | 103.4 ms | 129.3 ms | FPGA Atrix-7 | 200 MHz, 8 cores | 3.24 ms | 6.47 ms | 9.70 ms | 12.93 ms | 16.16 ms | MATLAB Core i7 | 4.6 GHz, 4 cores, 8 threads | 74.5 ms | 146 ms | 198 ms | 265 ms | 363 ms | MATLABRyzen 5 | 4.0 GHz, 6 cores, 12 threads | 73.1 ms | 138 ms | 206 ms | 274 ms | 353 ms | MATLABPentium | 3.3 GHz, 2 cores, 2 threads | 155 ms | 300 ms | 451 ms | 607 ms | 757 ms |
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Table 2. Time differences of calculating FFT between FPGA and Matlab
Performance | Data frame write to read | FFT process | FFT frame write to read | PCIe FIFO depth |
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Worst | 592(lines) | 9259732(cycles) | 1(frame) | 15106 | Limit | 2000(lines) | 10000000(cycles) | 3(frames) | 65535 | Headroom /% | 70.4 | 7.4 | 66.7 | 76.9 |
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Table 3. Real-time test results
Process | Data read | FFT calculate | All |
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Clock consume | 6674732(cycles) | 2585000(cycles) | 9259732(cycles) | Utilization /% | 72.1 | 27.9 | 100 |
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Table 4. Time analysis of secondary pipeline