The scaling of conventional MOSFET introduces various short channel effects in the nanoscale that needs to be addressed to assure the optimum performance of any device^{[1, 2]}. The FinFET device has recently attracted attention due to superior electrical properties at sub-22 nm technology nodes. It has better channel control than the conventional MOSFET structure^[3]. Various novel devices have been investigated to diminish the short channel effects, such as double gate TFET^[4], double gate and tri-gate FinFET^[5], omega FinFET^[6], and junctionless FinFET^[7]. A junctionless transistor (JLT) is an emerging concept with simple fabrication steps compared to conventional MOSFETs because, in the junctionless FinFET, the source, channel, and drain have constant concentrations. The other difference between a junctionless FinFET and a conventional MOSFET is that the drain current flows through the bulk of the semiconductor in a junctionless FinFET and flows through the channel in a conventional MOSFET^{[8, 9]}.

Another solution to minimize the short channel effects is to employ beyond silicon materials, for example, Ge, SiGe, GaAs, and group Ⅲ−Ⅴ materials. W T Chang et al.^[10] presented the threshold voltage shifting and transconductance with the strained SiGe channel dimension variation. R Das et al.^[11] proposed the structure of the tri-gate heterojunction FinFET with various configurations of the gate dielectric and metal stacks. It was found that the junction formed between Ge and Si produces a lower leakage current than conventional MOSFETs, but it had more subthreshold swing (SS). M J Kumar et al.^[12] reported the strain effect on the threshold voltage (V_t) of strained Si/SiGe MOSFETs using the mathematical model. It also discussed the effect of germanium content on V_t of the bulk MOSFET. T V Singh et al.^[13] presented the impact of Ge content in the SiGe channel in a cylindrical MOSFET.

V. Venkkataraman et al.^[14] derived the expression of threshold voltage considering the Si strain effect on the SiGe channel. Fei Ding et al.^[15] proposed a p-channel FinFET with a heterogeneous channel region (Si-Si_0.9Ge_0.1) and compared it with a conventional p-channel FinFET. It was observed that the hetero-channel structure provides more ON current than the conventional one, and a low Ge mole fraction can enhance performance.

The objective of this manuscript is to analyze the performance of the device with a channel stack using a compound semiconductor material. Various studies have been presented in the literature to analyze the digital, analog/RF and linear characteristics of FinFET and junctionless devices^{[16, 17]}. However, according to our research, the performance evaluation of tri-gate junctionless FinFET with a SiGe based stack channel, is required to analyze the analog/RF and linearity parameters. Since modern communication systems operate in the gigahertz frequency range and require low intermodulation linear operation for detecting the weak signal, the linearity parameters play a vital role in high frequency domain.

Key contributions in the proposed work: In the manuscript, the following objectives are setups for the tri-gate junctionless FinFET device:

(1) Channel stack engineering in the SOI junctionless tri-gate FinFET.

(2) Analysis of digital parameters for different channel stacks of the device.

(3) Analysis of RF/analog and linearity parameters.

(4) The comparison with the existing devices presented in the literature.

The other sections in the manuscript are categorized as follows: Section 2 narrates the simulation setup, the device structure is presented in Section 3, Section 4 represents the general fabrication flow of the device, and Section 5 is the results and discussion that include the analysis of the proposed structure for digital, analog applications and linearity performance. Finally, Section 6 concludes the manuscript.

Cogenda Genius VisualTCAD software is utilized for structure simulation^[18]. Since the device is heavily doped, the Lombardi and Philips mobility models are considered for the simulation of Si and SiGe materials, respectively. Eq. (1) represents the Lombardi surface model mobility equation^[18]:

1μt=1μb+1μac+1μsr,(1)

where μt is the total mobility, μb is the doping-dependent bulk mobility that occurs due to ionized impurity scattering, μac is the mobility degradation resulting from acoustic phonon scattering, and μsr represents the mobility degradation due to surface roughness scattering.

The Philips mobility model for the SiGe material given as Eq. (2)^[18].

1μ0,n=1μLattice,n+1μD+A+p,(2)

where μ0,n is the electron mobility, μLattice,n is the electron mobility due to lattice scattering, and μD+A+p is the mobility due to donor (D), acceptor (A), screening (p).

The hot carrier model is considered to assess the effect of hot carriers. The Schokley-Read-Hall (SRH) model is used to incorporate carrier generation and recombination. The parameters, for example, the Drift-Diffusion model, and Poisson equation solver, are also defined for the simulation. The Drift-Diffusion model solves the Genius code of the device for constant lattice temperature. Its main function is to solve the partial differential equation, known as the Poisson equation, along with the continuity equation of charge carriers^[18]. The VisualTCAD Genius tool uses the following Poisson’s equation to solve the partial differential Eq. (3) of the device^[18],

∇⋅(ϵ∇ψ)=−q(p−n+ND+−NA−),(3)

where ψ represents the electrostatic potential of the vacuum level, p and n are the hole and electron concentrations, respectively, ND+, NA− are the impurity concentrations, and q is the charge of the electron.

The tool is calibrated as per the data presented in Ref. [19]. The physical specifications such as electron mobility (µ₁), exponent of the bulk term of the Lombardi surface mobility model (α), and doping parameter (CSN.LSM) are carefully modified to match the experimental data reported in Ref. [19]. These parameters are taken as: EXN1.LSM (α) = 0.8, MUN1.LSM (µ₁) = 50 cm²/(V·s), CSN.LSM = 3.4 × 10²⁰ cm⁻³. For SiGe material, Philips model is used to simulate the device.

Fig. 1(a) represents the simulated calibration against the reported experimental data^[19] at V_DS = 0.9 V. It depicts that the experimental data in Ref. [19] matches with the simulated data calculated using VisualTCAD Genius simulation. In the graph, the drain current is taken in the log scale and V_GS is varied up to 1 V. For the calibration, the gate length is taken as 26 nm, Fin height is 29 nm, Fin thickness is 10 nm and equivalent oxide thickness (EOT) for high-k dielectric is 1 nm, as per the experimental data presented in Ref. [19] for Si material. Fig. 1(b) depicts the percentage change in the simulation data of I−V curve with the experimental data reported in Ref. [19]. In this curve, the error bars represent the deviation of simulated data with experimental data and there is 3%−5% variation between both data. Fig. 1(c) is the general cross-sectional representation of the junctional FinFET device with different dimensions. The device consists of HfO₂ as the high-k gate dielectric material, spacers (HfO₂) to suppress the source/drain−gate capacitances, and metal (work function = 4.9 eV) for the gate electrode. Fig. 2 represents the simulation flow of the device in VisualTCAD. It starts with defining the parameters such as Fin height, thickness, oxide thickness, source/drain length, spacer length, gate length. The script of the device is written in the VisualTCAD text editor and meshing is defined.

Fig. 3(a) represents the proposed structure of the device with Tri layer Stack Channel (TLSC) used for simulation; the channel is formed as the stack of Si + Si_0.75Ge_0.25 + Si (here, Si_0.75Ge_0.25 represents that the mole fractions of Si and Ge are 0.75 and 0.25 respectively), here, the SiGe layer is between the layers of Si, so the top and bottom of the Fin have same layers. Fig. 3(b) is the 2D view of the channel with double layer stack channel (represented as DLSC); in this, the channel is the combination of Si + Si_0.75Ge_0.25, Fig. 3(c) illustrates the 2D front view of the single layer channel (Si Channel). The height of the layers is equally divided in the DLSC and TLSC. The other parameters such as gate length, source/drain length, Fin thickness, spacer length are shown in Table 1. The doping concentration of source, drain and channel is 1 × 10¹⁹ cm⁻³. The simulated 3D view of the proposed device is presented in Fig. 3(d). According to the width quantization rule, the effective width (W_eff) of the device that is given as 2HFin+TFin^[20].

Figs. 4(a)−4(c) represent the contour plots of the valence band (VB) and conduction band (CB) energy for the structures TLSC, DLSC, and SLC, respectively, which is obtained at V_DS = 0.7 V. The figure shows the variation of energy VB and CB along the channel and Fin height. Since the channel stack is different for the three structures; only the energy variation in the channel is shown here. Figs. 4(a)−4(c) show that the energy increases with negative magnitude along the channel for the three structures and the lowest difference between CB energy and VB energy is obtained for the TLSC structure, which is shown graphically in Fig. 4(d). It depicts the energy-band diagram of the three structures (TLSC, DLSC, SLC), based on the contour plot and it is plotted for source, channel and drain regions. The figure shows that the band-gap for SLC, DLSC and TLSC structures in the source and drain region is approximately the same due to the same material (silicon) but it is different in the channel region due to stacking of the materials in the three structures. The band-gap for SLC is 1.1 eV, for DLSC, 0.89 eV and for TLSC, 0.85 eV, approximately. The CB in TLSC has a steeper slope than DLSC and SLC from the source−channel to the channel−drain region; this increases the electron flow from source to drain and increases the drain current.

Fig. 5 represents the general process flow of the device. It starts with the preparation of the Si wafer (Fig. 5(a)), after that the SiO₂ layer is deposited on the Si substrate using thermal oxidation (Fig. 5(b)). After this, the SOI layer is deposited and the Si layer is formed as shown in Figs. 5(c) and 5(d). After the formation of the Si layer, the SiGe-Si stack is fabricated (Figs. 5(e) and 5(f)). The stack of the Fin is patterned using electron beam lithography as shown in Fig. 5(g). The gate stack (HfO₂ oxide-gate material) is formed as shown in Figs. 5(h) and 5(i). After that ion implantation (n+) is done to form source and drain regions (Fig. 5(j)). Then, the HfO₂ layer is deposited on the spacer regions (Fig. 5(k)).

This section analyses the performance of SLC, DLSC, and TLSC. The height of the Fin (H_Fin) is taken as 36 nm, and the Fin thickness (T_Fin) is taken as 7 nm for the three structures. The digital parameters such as SS, DIBL, I_ON/I_OFF and RF/Analog parameters: transconductance parameter (g_m), transconductance generation factor (TGF), output transconductance (g_ds), voltage gain (A_v), cut-off frequency, maximum oscillation frequency and linearity parameters are compared for the three structures at gate length (L_G) 20 nm and supply voltage 0.7 V. The parameters are taken according to the IRDS-2021 “5 nm” node-range^[21].

To compare the conduction mechanism, Fig. 6 shows the electron density distribution in the three structures along the channel at the ON state (V_GS = 1 V) and V_DS is taken as 0.7 V. Fig. 6(a) represents that TLSC has two Si–SiGe junctions and its electron density is higher than the DLSC structure shown in Fig. 6(b), which has one SiGe−Si junction. Fig. 6(c) depicts the electron density distribution in the SLC structure along the channel and it is uniform throughout the height of the channel. The electron density in the SLC is lower than the DLSC and TLSC as it has only one silicon layer in the channel.

Fig. 7(a) represents the current−voltage (I−V) characteristics of SLC, DLSC, and TLSC structures. It shows that the TLSC structure has more drain current (I_ON) than the other structures (DLSC and SLC) due to the hetero-layer of Si−Si_0.75Ge_0.25−Si. In the TLSC structure, the SiGe layer is between the two Si layers, which creates two Si−SiGe junctions and the strained lattice structure that can enhance carrier mobility. When the Si channel is strained, the spacing between the energy band is altered, as shown in Eq. (4). This can lead to the effective mass of the electrons, which can enhance their mobility. When a voltage is applied to the gate of the FinFET, an electric field is generated that controls the flow of carriers through the channel region. The higher mobility of carriers in the TLSC allows for more efficient flow of carriers though the channel, leading to a higher drive current. As Fig. 6(a) shows that TLSC has high electron density due to two Si−SiGe junctions, the resulting drain current is shown in Fig. 7(a).

The parameters related to SiGe such as modified band gap and density-of states, are given in Eqs. (4)−(6)^[22]:

ΔEG(SiGe)=0.467x,(4)

NV(SiGe)=(0.6x+0.04(1−x))×1019cm−3,(5)

ϵ(SiGe)=11.9+4.2x,(6)

where ΔEG(SiGe) represents the reduction in the SiGe band gap from Si, NV(SiGe) is the density-of-states in valence band, ϵ(SiGe) is permittivity of SiGe, and x is the mole fraction of Ge. The modification in band gap of SiGe causes the increase in mobility, hence drain current increases. The drain current in TLSC is more than DLSC and SLC because it has two Si−SiGe junctions.

The value of the drain current for the TLSC is 0.342 mA/µm, for DLSC is 0.28 mA/µm and for SLC is 0.299 mA/µm. The logarithmic plot is also shown in Fig. 7(a); it represents that the SLC structure has the lowest OFF current (I_OFF) and DLSC, TLSC structures have an almost equal OFF current but more than SLC. This is because the SiGe layer in DLSC and TLSC induces strain in the channel region, which enhances the diffusion of dopants and increases the formation of the leakage path. Additionally, TLSC and DLSC typically have higher parasitic capacitances due to additional interfaces in the channel structure, which increases the tunnelling current and contribute to the overall leakage current.Fig. 7(b) represents the comparison of I_OFF and I_ON/I_OFF, representing that SLC has less I_OFF, more I_ON/I_OFF than DLSC and TLSC, but these structures have I_ON/I_OFF more than 10⁶, which is required for better performance of a device according to IRDS-2021^[21]. These values are obtained at V_DS = 0.7 V and V_GS is varied from 0 to 1 V.

The mathematical expression for SS is given below in Eq. (7)^[5]. The SS is a current−voltage characteristics that determines the transistor’s behaviour in sub-threshold region. It represents the measure of how fast a transistor can be turned ON/OFF. Its value is limited by thermal voltage (kT/q), which results in the limit of SS value at 60 mV/dec. To perform a device effectively, the SS value must be near to 60 mV/dec. In this paper, the value of SS for TLSC, DLSC and SLC are 62.29, 62.34, and 61.64 mV/dec respectively, at fixed drain bias 0.7 V. The SS values of SLC, DLSC, and TLSC structure are compared with other devices presented in the literature, as shown in Table 2.

SS=[dlog(ID)dVGS]−1=ln(10)kTq(1+CdCox),(7)

where C_d is known as depletion capacitance, C_ox is the oxide capacitance, and kTq is the thermal voltage.

The DIBL is another parameter of the short channel effect which refers to threshold voltage reduction at higher drain bias. The value of the DIBL must be low for the better device operation. The DIBL is calculated by measuring the horizontal shift in sub-threshold characteristics divided by the change in drain voltage. The equation for the DIBL is given in Eq. (8)^[5]. The values of the DIBL obtained by simulation for the three structures are given in Table 2 and these values are 29.6, 32.2, and 28.07 mV/V for the TLSC, DLSC and SLC structures, respectively.

DIBL=|Vth,lin−Vth,sat|VDS,sat−VDS,lin,(8)

where V_th,lin, V_DS,lin are threshold voltage and drain−source voltage in linear region, respectively, and V_th,sat, V_DS,sat are threshold voltage and drain−source voltage in the saturation region, respectively.

The performance analysis of the three structures is given in Table 2 and compared with other reported papers. The table compares the ON current (I_ON), OFF current (I_OFF), I_ON/I_OFF, SS, DIBL and V_t of the different structures. For comparison, the gate length is taken as 20 nm for TLSC, DLSC and SLC structures. The Table 2 shows that SiGe material stack channel has more ON current, more I_ON/I_OFF, less SS and DIBL than the reported papers. Hence, SiGe material-based stack channel improves the short channel effects.

The impact of channel structures on SS, DIBL, and threshold voltage (V_t) is shown as a bar graph in Fig. 8. It illustrates that TLSC has less V_t than the SLC but almost the same as the DLSC, because the SiGe layer in the channel, effectively increases the carrier mobility due to the strain effect; as a result, the ON current is higher and resulting in less V_t. In Fig. 8, the values are taken for V_DS = 0.7 V.

In this subsection, RF and analog parameters such as g_m, g_ds, TGF, f_T, f_max, gain, gain-frequency product (GFP) are evaluated and compared for the three structures. Eqs. (9) and (10) represent g_m and TGF, respectively^[26]. Transconductance plays an essential role in the analysis of a circuit, and represents the change in drain current (I_D) with gate voltage (V_GS) at fixed drain bias. TGF demonstrates how effectively the current can attain the g_m value.

gm=∂ID∂VGS,(9)

TGF=gmID.(10)

The variation of g_m and TGF for the three structures are shown in Fig. 9. The transconductance is a measure of how effectively the device can amplify an input signal. It is related to the carrier mobility or drain current. Since the TLSC structure provides more drain current due to higher mobility; the electron can move more easily through the channel and respond more quickly to changes in the gate voltage, and it leads to higher g_m. From Fig. 9, it is observed that the TLSC has the highest value of g_m due to the Si−SiGe−Si stack channel. Here, the maximum value of g_m is obtained in a moderate-to-strong inversion region, where the channel resistance changes rapidly with the V_GS. In this region, small changes in V_GS can result in large changes in drain current, which means the device can provide high g_m. Fig. 9 also represents the TGF value for the three structures with respect to the gate voltage. It shows that the TGF has almost the same value in the strong inversion region, it only changes in-subthreshold region. The value of g_m in the DLSC structure starts decreasing than SLC structures at a higher gate voltage, because the device is tri-gate and the gate is controlling the tri-layer stack channel (TLSC) equally in three directions (the top and bottom have the same layers), but in the DLSC, the top, and bottom of the FinFET have different layers; this asymmetric structure reduces the current in the double-layer stack channel, resulting in a decrease in g_m. Eq. (11) represents the output transconductance (g_ds)^[26]; it is the rate of change of drain current with drain-source voltage (V_DS) and determines the driving capability of a device^[26]. The inverse of g_ds is known as output resistance (R_o). Fig. 10 shows the g_ds for three types of channel structures. Initially, g_ds is high in the linear region and starts decreasing with V_DS. It achieves a constant value in the saturation region. Fig. 10 also shows that the TLSC structure has a maximum value of g_ds at V_DS = 0 and decreases gradually with an increase in V_DS. The presence of SiGe in the channel region of the stacked channel FinFET increases the electron mobility, resulting in higher output transconductance in the TLSC and DLSC structures. This is because the electrons experience less resistance to their motion, and are able to flow more freely through the channel region. The output transconductance is obtained at a fixed gate voltage.

gds=∂ID∂VDS.(11)

The intrinsic gain (g_m/g_d) represents the amplification factor which should be high to enhance the analog performance. Eq. (12) represents the expression for intrinsic gain; it is the ratio of g_m and g_ds^[26]. Fig. 11(a) shows variation of gain with gate voltage for the three types of channel structures. The peak value of gain is the highest for the TLSC structure because it has higher transconductance (g_m) than the other structures due to higher ON current. The DLSC structure has less gain than SLC due to less g_m. The gain value falls at a higher gate voltage, known as mobility degradation, due to the scattering of charge carriers.

Intrinsicgain(AV)=gmgds.(12)

The cut-off frequency (f_T) and maximum oscillation frequency (f_max) are other crucial figure-of-merit characteristics for the high-frequency performance of transistors. The frequency at which short-circuit current gain becomes one is known as cut-off frequency (f_T) and it is the ratio of small signal output current to input current when the output is short-circuited. The expression of f_T is given in Eq. (13)^[26], it shows that f_T is directly and inversely proportional to g_m and C_gg, respectively, which means the higher the g_m or lower the C_gg, the higher the cut-off frequency. The expression of the gain-frequency product (GFP) is given in Eq. (14)^[26]. It is an essential parameter for high-frequency applications.

fT=gm2πCgg,(13)

where C_gg is the total gate capacitance represented as the total of gate–source capacitance and gate–drain capacitance (C_gs + C_gd).

GFP=AV×fT.(14)

The frequency at which unilateral power gain equals unity is known as maximum oscillation frequency (f_max). Therefore, it is also known as the highest frequency at which a transistor can still provide power gain. It signifies the practical upper limit for the useful performance of a device. Higher f_max means that the device can produce oscillations at a higher frequency. The mathematical expression for f_max is given in Eq. (15)^[27].

fmax=fT4Rg(gds+2πfTCgd),(15)

where R_g is the series resistance, which is represented as (Eq. (16))^[27]

Rg=1qμND+2LS/DHFinWeff,(16)

where q represents electron charge, µ is the career mobility, N_D⁺ is the doping concentration, L_S/D denotes the source/drain length, H_Fin is the Fin height and W_eff is the effective width, which is represented as 2H_Fin + T_Fin.

The devices with f_max > f_T, provides power gain at frequencies of more than f_T and up to f_max, thus, these can be used as power amplifiers between frequency range f_T and f_max. The devices with f_max > f_T, can only achieve power gain up to f_max and cannot be utilized for the amplification of power between f_max and f_T^[30].

The f_T variation with V_GS for the SLC, DLSC, and TLSC is shown in Fig. 11(b), indicating that the TLSC structure has high cut-off frequency than the other structures. Since the f_T depends directly on g_m; the TLSC structure provides more g_m, resulting in high f_T. The cut-off frequency in DLSC decreases at a higher gate voltage due to reduction in g_m, as shown in Fig. 9. Fig. 11(c) represents the variation of the GFP with V_GS; it depicts that GFP increases with an increase in the gate voltage and the TLSC structure has a maximum value of GFP due to high g_m and gain. The GFP attains its maximum value in the inversion region due to higher drain current and g_m. Fig. 11(d) represents the variation of f_max with gate voltage. The obtained curve is almost similar to the f_T−V_GS curve, except the frequency values are different. It represents that the TLSC structure has more maximum oscillation frequency, which means that it can provide more power gain than the other two structures. The comparative analysis of analog/RF parameters of the different structures is given in Table 3. It compares the analog parameters g_m, TGF, g_ds, f_T, f_max and gain of the TLSC, DLSC and SLC structures with the junctionless FinFET devices presented in the literature at 20 nm gate length.

The analysis of linearity parameters for the stack-based channel is also done in this manuscript. The linear performance parameters deal with the non-linear distortion of the device that describes the non-linear relationship between input and output, resulting in mobility degradation that changes the transconductance performance. The major disturbances in the communication systems are higher-order transconductance parameters g_m2 and g_m3, also known as harmonic distortions. The expressions for these are given in Eqs. (17) and (18); these are the second and third-order derivative of I_D with respect to V_GS, respectively^[31].

gm2=∂2ID∂VGS2,(17)

gm3=∂3ID∂VGS3.(18)

The variation of g_m2 and g_m3 with V_GS is shown in Figs. 12(a) and 12(b). The lower peak value of g_m2 and g_m3 signifies that the device has better linearity or less distortions. Figs. 12(a) and 12(b) represent that the peak values of g_m2 and g_m3 for DLSC and TLSC structures are less than SLC, which means that DLSC and TLSC have fewer harmonic distortions than SLC, hence SiGe based hetero-structures improve the linearity of a device. This is because, higher drain current can reduce the variation of g_m by decreasing the impact of parasitic resistances. Additionally, at higher drain current, the channel becomes wider and electric field becomes more uniform. This uniform electric field leads to more uniform current density, resulting in a more linear transconductance. The values of g_m2 and g_m3 are high at lower gate voltage and it decreases with an increase in V_GS, because the g_m decreases at higher gate voltage due to higher drain current and consequently the magnitude of second and third-order harmonics decreases.

Another parameter for linearity is the voltage intercept points (VIP₂ and VIP₃). The VIP₂ is the gate voltage representing the equal values of the fundamental harmonic and the second-order harmonic and VIP₃ is the gate voltage representing the same values of the fundamental and third-order harmonics. The expressions are given in Eqs. (19) and (20)^[31]:

VIP2=4gmgm2,(19)

VIP3=24gmgm3.(20)

Figs. 13(a) and 13(b) illustrate the variation of VIP₂ and VIP₃ for the three structures with V_GS. The peak of VIP₂/VIP₃ signifies the improvement in linearity performance. Fig. 13(a) depicts that the SLC and DLSC have an almost the same peak value of VIP₂, which is more than the TLSC; Fig. 13(b) represents that TLSC has the highest value of VIP₃ and the value decreases for DLSC than SLC in the strong inversion region due to the channel asymmetry. The values of VIP₂ and VIP₃ increase at a lower gate bias and become constant for the three structures at the higher gate voltage after getting the maximum values. Fig. 13(b) also represents that TLSC shows better linear performance at third harmonic distortion (VIP₃) and DLSC, SLC shows better linearity at second harmonic distortion (VIP₂).

Another fundamental factor for linearity performance is the 1-dB compression point that determines the power level at input and output. It is the measure of the magnitude of the input power to fall the output power by 1-dB and the equation is given in Eq. (21)^[31].

1 dB compression point=0.22gm/gm3.(21)

It specifies the power level that results in 1-dB gain drop from a small signal value. The factor is vital for an amplifier as it provides a clear idea of the maximum power on which a device can operate at a fixed value of gain.

The peak transmitted power is kept below the 1-dB compression point to prevent inter-channel interference. Therefore, the high value of the point improves the linearity. Fig. 14 represents the comparison of peak values of 1-dB compression points for the three structures. It shows that the TLSC has the highest peak value of 1-dB compression point which means that it provides more linearity than the other structures. The value of the 1-dB compression point for the DLSC is less than the other two structures due to the lower drain current. There is a 52.8% increment in peak value for the SLC structure than the DLSC and a 21.4% increment for the TLSC than the SLC, as shown in Fig. 14.

A detailed study of the tri layer stack channel, double-layer stack channel and single layer channel is presented in this work. For the analysis, various parameters such as I_ON, I_OFF, I_ON/I_OFF, SS, DIBL, V_t are extracted using the VisualTCAD simulation. The result shows that the tri-layer stack channel has a high I_ON and V_t when compared with the other structures. The analog and RF parameters: g_m, g_ds, gain, TGF, f_T, GFP are also calculated for further study and it shows that the tri layer stack channel (TLSC) is more suitable for analog applications due to its high g_m, gain, cut-off frequency and maximum oscillation frequency. The increase in peak value of g_m of TLSC is 11.9% to SLC and 29.3% to DLSC. In addition, compared to SLC and DLSC, in TLSC, the peak value of gain increases by 16.3% and 48.44%, respectively. The increase in peak value of the cut-off frequency of TLSC is 7.2% more than SLC and 34.8% more than DLSC. The linearity parameters for analysing the distortion are also discussed and the results represent that TLSC shows better linearity than the other structures due to improved transconductance.