A readout structure with double column buses and shared source follower for IRFPAs

Yu-Ze NIU; Ya-Jun ZHU; Wen-Gao LU; Yu-Ting GU; Ya-Cong ZHANG; Zhong-Jian CHEN

doi:10.11972/j.issn.1001-9014.2020.03.010

Abstract

A new readout circuit structure for infrared focal plane array with pixel-level shared source follower and double column buses is proposed in this paper. The voltage signal of the pixel is transferred through double column buses instead of single column bus, and therefore the non-uniformity and non-linearity caused by the parasitic resistor of the column bus is eliminated. By sharing the source follower within four adjacent pixels in the same column, the aspect ratio (W/L) and area of the source follower are increased to suppress the thermal noise, flicker noise and non-uniformity caused by process. A 640×512 readout circuit using this structure is designed and fabricated in 0.35μm 2P3M CMOS process and the pixel pitch is 15μm. The test results indicate the readout circuit receives a high dynamic range (DR) of 81dB high-quality infrared images with a low power consumption of 30mW. The nonlinearity is 0.11%, and the non-uniformity is less than 1%. Medium-wave infrared detector assembly is fabricated and tested. The assembly’s non-uniformity is less than 5% and the NETD is 18mK. High-quality infrared images are obtained.

Keywords

double column buses IRFPA ROIC shared source follower

Introduction

Infrared imaging systems are widely used in the national defense, science, medical and industrial fields [1, 2, 3] . The infrared focal plane detector assembly is the core of the infrared imaging system, which consists of a photodiode array and a readout circuit interconnected by indium bumps [4, 5] . The readout circuit achieves the amplification and acquisition of the photodiode array signals, and has a significant impact on the performance of the infrared imaging system [6, 7, 8] . With the development of infrared imaging system, the scale of the detector array is increasing and the pixel pitch is decreasing. As a result, the non-uniformity and nonlinearity of the array are gradually increasing due to process fluctuation and parasitic effect [9] . Meanwhile, the shrinking pixel pitch also results in a challenge to high signal-to-noise ratio (SNR) [10, 11] .

The pixel circuit in the readout circuit is directly connected to the photodiode to integrate the photocurrent. Two modes are typically used to readout the pixel signal: charge readout mode [7, 9] and voltage readout mode [12, 13, 14, 15] . In the charge readout mode, with the increase of the array size, the parasitic capacitance of the column bus becomes larger and degrades the SNR when the signal is transferred from pixel to column. Accordingly, the charge readout mode is not suitable for a large-scale readout circuit [16] . In the voltage readout mode, an op-amp or a source follower (SF) is needed in the pixel to transfer the signal from pixel to column. However, the small pixel size limits the area of the op-amp or source follower, which results in poor noise performance [16, 17] . Moreover, the non-uniformity introduced by process fluctuations will increase due to the increase of the array scale [18, 19, 20, 21] .

This paper proposes a new voltage readout structure to solve the problems mentioned above. The signal is transferred from pixel to column by double column buses instead of single column bus, reducing the non-uniformity and the nonlinearity caused by the parasitic resistor of the column bus. The source follower within four adjacent pixels in the same column is shared to increase the area and the aspect ratio. Therefore the non-uniformity and noise are reduced.

The content of this paper is as follows. Section 1 will introduce the new structure and operating principle of the proposed readout circuit, focusing on the analysis of double column buses readout mode and the four-pixel-shared source follower. And simulation results are presented as well. Section 2 will present the test results and imaging experiment. The conclusion will be given in Section 3.

1 The structure and principle of the readout circuit

1.1　Conventional readout circuit structure

The conventional 640\times512 readout circuit architecture with voltage readout mode is shown in Fig. 1 . The operating principle of the circuit is as follows. First, the pixel circuit converts the photocurrent into a voltage signal. Second, the voltage in the pixel circuit is transferred to column circuit row-by-row. Finally, the voltage in column circuit is sent off-chip through the output buffer column-by-column.

Figure 1.Block diagram of the 640×512 conventional voltage readout mode readout circuit.

The circuit of conventional voltage readout mode [13, 20, 22] is shown in Fig. 2 and single column bus is used to transfer signal from pixel to column. As the scale of the array increases, the length of the column bus is also increasing, and its parasitic resistor is gradually becoming non-negligible.

Figure 2.Circuit diagram of the conventional voltage readout mode readout circuit.

It can be seen in Fig. 2 that the sources of M1 and M2 are connected through the parasitic resistor of the column bus instead of connected directly. The parasitic resistor mainly includes the bus parasitic resistor (513-i)\times R U and the R on of the row selection switch, where R U is the parasitic resistor of a metal wire with the length of one pixel and i is row number. (513-i) is the number of the unit resistors which are connected in series and depends on the location of the pixel. Since the parasitic resistor of the column bus is network-like, (513-i) differs with different pixel, which results in different voltage drops of corresponding pixel signals. Therefore, the output V OUT will show a great spatial non-uniformity.

V_{O U T} (i, j) = V_{I N T} (i, j) - V_{g s, 1} - I_{0} \times (R_{o n} + (513 - i) \times R_{U}) + V_{g s, 2}

\approx V_{I N T} (i, j) - I_{0} \times (R_{o n} + (513 - i) \times R_{U})

The term of i\timesR U is increasing as the scale of the array increases and the entire array will show a greater spatial non-uniformity.

In the readout circuits [13, 20, 22], V INT of the pixel is read through the source follower in the pixel. As the pixel pitch decreases, the area of the source follower is decreasing, so the mismatch of the source followers within different pixels will result in a severe non-uniformity. Moreover, the area and W/L of the source follower are limited by the pixel area. Since the thermal noise and flicker noise of the source follower are the main sources of noise in the signal path, the noise from the pixel-column transmission is seriously affected by the pixel area.

1.2　The proposed readout circuit structure

To solve the above problems, a readout structure with pixel-shared source follower and double column buses transmission is proposed as shown in Fig. 3 .

Figure 3.Block diagram of the pixel-level shared-SF and double column buses readout circuit.

The pixel-column signal transmission is completed through two column buses, eliminating the non-uniformity caused by the parasitic resistor and the nonlinearity caused by the source follower. The four adjacent pixels in the same column share a source follower, increasing the W/L and area of the source follower. Thereby the thermal noise, flicker noise, and non-uniformity caused by process variations are reduced. The circuit diagram of the signal path is shown in Fig. 4 .

Figure 4.Circuit diagram of the pixel-level shared-SF and double column buses readout circuit.

The working principle is as follows. When RS<1> and RSW<1> is high, the voltage V S is transferred to the column circuit by the shared source follower of the four adjacent pixel circuits. Thus, the area and the W/L of the source follower is four times of that of one single pixel. When the switches M SA and M SB are turned on, the current through M1 flows into M3 through M SA and the column bus BUSA. Similarly, the current through M2 flows into M4. Hence there is no current flowing through M SB and the column bus BUSB and no additional voltage drop over the parasitic resistor of this signal path. The source voltages of M1 and M2 are equal. The output voltage is:

V_{O U T} (i, j) = V_{S} (i, j) - V_{g s, 1} + V_{g s, 2} - I_{0} \times 0 = V_{S} (i, j)

The proposed structure and the conventional structure are compared by simulation. The nonlinearity and non-uniformity caused by the parasitic resistors of column bus and MOS switch are simulated and the results are shown in Fig. 5 .

Figure 5.Simulation results of the output deviation of the conventional and the proposed structure

Shared source follower of four adjacent rows firstly reduces the local non-uniformity within four rows. It also increases the area of the source follower by four times and the macroscopic non-uniformity of the entire array can be reduced. Monte-Carlo simulations are performed to compare the non-uniformity of the conventional structure and the proposed structure. The simulation result is shown in Fig. 6 and the proposed structure has lower non-uniformity.

Figure 6.Monte-Carlo simulation results of the conventional and the proposed structure

The simulation results of Fig. 5 and Fig. 6 are summarized in Table 1 .

Structure

Nonlinearity

(Parasitic Resistor)

Non-uniformity

(Parasitic Resistor)

Non-uniformity

(Process Fluctuation)

conventional structure

2.78%

2.5%

1.67%

proposed structure

0.27%

<0.1%

<0.6%

Table 1. Comparison of the nonlinearity and non-uniformity between the conventional and the proposed structure

View all Tables

The pixel- shared source follower can reduce the noise as well as reduce the non-uniformity of the array. As shown in Fig. 2, the equivalent input noise introduced by the signal transmission from pixel to column is . It includes not only the noise of the source follower MOSFETs but also the noise of the current source MOSFETs. The current source MOSFETs in the column have less area limitation and their noise contribution can be designed to be negligible. The main noise source is the same size source followers of M1 and M2. can be simplified as follows:

\begin{array}{l} V_{n}^{2} \approx 2 \times (V_{n, t, M 1}^{2} + V_{n, \frac{1}{f}, M 1}^{2}) \\ \approx 2 \times (\frac{4 K T λ}{g_{m 1}} \times f_{1} + \frac{K_{n}}{C_{o x} W_{1} L_{1}} \times l n \frac{f_{1}}{f_{0}}) \end{array}

f 1 is the upper limit of the noise integration bandwidth, f 0 is the lower limit of the flicker noise integration. As shown above, the noise includes thermal noise and flicker noise. Since the readout circuit operates at the temperature of liquid nitrogen, the thermal noise is relatively small compared to the flicker noise. To reduce the flicker noise, it's necessary to increase the area of the M1 and M2. The source followers M1 and M2 are limited by the pixel area and the matching relationship respectively, so the flicker noise cannot be effectively reduced.

The proposed pixel circuit uses a shared source follower of four adjacent pixels in the same column, and the source follower’s area is increased by four times compared with the conventional structure. In this case, the equivalent input noise is:

\begin{array}{l} V_{n}^{' 2} \approx 2 \times (V_{n, t, M 1}^{' 2} + V_{n, \frac{1}{f}, M 1}^{' 2}) \\ \approx 2 \times (\frac{4 K T λ}{{g^{'}}_{m 1}} \times f_{1}^{'} + \frac{K_{n}}{4 C_{o x} W_{1} L_{1}} \times l n \frac{f_{1}^{'}}{f_{0}}) \end{array}

Since the frequency range of noise integration can be adjusted by the loading capacitance, f 1 and f 1' can be equal. The ratio of to is k. If the source follower MOSFETs of both structures work in the saturation region, k is approximately 2. If the source followers work in the sub-threshold region, k is slightly less than 2.

{g^{'}}_{m 1} = k \times g_{m 1}

The ratio of the equivalent input noise of the two structures is as follows:

\begin{array}{l} \frac{V_{n, t r a n}}{V_{n, t r a n}^{'}} \approx \sqrt[]{\frac{2 \times (V_{n, t, M 1}^{2} + V_{n, \frac{1}{f}, M 1}^{2})}{2 \times (V_{n, t, M 1}^{' 2} + V_{n, \frac{1}{f}, M 1}^{' 2})}} \\ = \sqrt[]{\frac{V_{n, t, M 1}^{2} + V_{n, \frac{1}{f}, M 1}^{2}}{\frac{V_{n, t, M 1}^{2}}{k} + \frac{V_{n, \frac{1}{f}, M 1}^{2}}{4}}} > \sqrt[]{k} \end{array}

It can be seen that when source-followers in n pixels are shared, the area increases by n times, the flicker noise reduces to 1/ the thermal noise reduces significantly because of the increase of g m .

2 Experimental results

Based on the proposed structure of shared source follower and double column buses, a readout circuit for medium-wave infrared imaging system is designed and fabricated using a 0.35μm 2P3M CMOS process. The array size is 640\times512 and the pixel pitch is 15μm. The supply voltage is 3.3V. Fig. 7 shows the photograph of the readout circuit chip.

Figure 7.Photograph of the 640×512 readout circuit chip.

The readout circuit has two operation modes: integration while read (IWR) mode and integration then read (ITR) mode. Fig. 8 shows the test results of noise and nonlinearity in IWR mode. Fig. 8 (a) shows the output rms noise with different integrated charge, and Fig. 8 (b) shows the nonlinearity of different V INT . As we can see from Fig. 8, the noise of the readout circuit is less than 0.2 mV, and the nonlinearity is 0.11%. The dynamic range (DR) is calculated from noise and output swing to be 81 dB. The non-uniformity is tested to be less than 1%. The output buffer of the readout circuit adopts the circuit structure in Ref.[24], which significantly reduces the power consumption while increases the output rate. The total power consumption of the readout circuit is only 30 mW.

Figure 8.Test results of the readout circuit in IWR mode: (a) noise, (b) nonlinearity

The readout circuit is interconnected with mercury cadmium telluride (MCT) detector array by indium bumps, and the detector assembly is tested at the temperature of liquid nitrogen. The NETD is 18 mK and the non-uniformity is less than 5%. An infrared image captured by this assembly is shown in Fig. 9 .

Figure 9.Imaging result of the infrared imaging system.

The performance parameters of the readout circuit and imaging system are compared with other literatures in Table 2 . It can be seen that our work has obvious advantages in terms of noise and power consumption.

Parameters	[23]	[11]	[20]	This work
Pixel size	15 μm×15 μm	15 μm×15 μm	7.5 μm×7.5 μm	15 μm×15 μm
Array size	640×512	640×512	640×512	640×512
Process	N/A	0.35μm CMOS	0.18μm CMOS	0.35μm CMOS
Power	50 mW	60 mW	N/A	30 mW
Charge handling capacity	5.0 Me^-	6.6 Me^-	3.1 Me^-	7.0 Me^-
NETD	25 mK	20 mK	25.5 mK	18 mK
Frame frequency	100 Hz	100 Hz	100 Hz	120 Hz

Table 2. Comparison of the performance parameters of readout circuits

View all Tables

3 Conclusion

This paper presented a new readout structure for infrared focal plane array. The voltage signal is transferred from pixel to column by double column buses instead of a single column bus. The non-uniformity and the nonlinearity caused by parasitic resistor of column bus are eliminated. The source follower MOSFET is shared within four adjacent pixels. The transconductance and area of the source follower are increased and the thermal noise, flicker noise, and non-uniformity caused by the source follower mismatch are suppressed. A readout circuit using this structure is designed and fabricated in 0.35μm 2P3M CMOS process. It is assembled with mercury cadmium telluride (MCT) detector array and high-quality infrared images are obtained.

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