Abstract
1. Introduction
The demand for analog/mixed-signal (AMS) integrated circuits (ICs) has been increasing in various emerging applications, including the internet of things (IoT), 5G networks, advanced computing, and healthcare electronics. Therefore, a short turnaround time of analog IC design is desired. However, while the automation algorithms have been significantly improved over the past decades, implementing analog layout is still a manual, time-consuming, and error-prone task.
Despite the continuous efforts in analog layout automation, those achievements have not been well adopted in current industrial flows. The main reason is rooted in the characteristics of AMS circuits. AMS IC design is a complex task due to the high design flexibility. Compared to its digital counterpart, AMS design is considered complicated since it deals with a wide range of specific circuit classes, various device types, and requires a customized tuning for each circuit class. Besides, analog layouts are sensitive to signal couplings, layout-dependent effects, and process variations. The circuit performance could suffer from significant degradation with minor changes in the layout implementation. Furthermore, there lacks an effective way to model the layout effects on analog performance, which imposes significant challenges for automation tools.
While analog electronic design automation (EDA) tools are far behind their digital counterparts, the endeavor to automate analog layout design can be traced back to decades before. One of the early analog EDA efforts, ILAC[
Promising advancements have been made in recent years. Strategies for designing analog circuits that are more synthesis-friendly have been proposed. Frameworks utilizing procedure-based layout techniques have been demonstrated. Also, optimization-based layout generation methods have been presented.
This paper aims to overview current AMS layout automation approaches and research trends and new visions on analog layout automation. Specifically, we will first review three primary AMS layout methodologies and related frameworks in Section 2. We then introduce several recent advances in academia with an emphasis on algorithms featuring machine learning (ML) and statistics in Section 3. We will finally present our visions on the open questions and trends in future EDA development for AMS layouts.
2. Current approaches and challenges
People have proposed different paradigms with various degrees of generality for different usage scenarios. However, introducing design-dependent strategies and prior knowledge in the automation flow often benefit the flow effectiveness in the cost of jeopardizing the generality of flow. In this section, we review three popular paradigms in the order of increasing generality.
(1) Synthesis-friendly AMS circuits: Design highly digital and modularized AMS circuits that are suitable for commercially available digital physical design tools.
(2) Procedure-based layout generation: Generate layouts based on the pre-designed templates in a procedural approach.
(3) Optimization-based layout synthesis: Formulate the layout generation as a constrained optimization problem and tends to model the layout quality as the objectives.
2.1. Synthesis-friendly analog circuits
In the past decade, enormous efforts have been devoted to improving the AMS circuits synthesizability. In the typical synthesis-friendly design flow, as shown in Fig. 1, a design database, including synthesizable analog blocks and architectures, is provided by the designer. By combining it with digital physical design methodologies, this flow aims to generate layouts using commercially available digital auto place and route (APR) tools, thus significantly improving design efficiency. This methodology leaves significant efforts in the design database generation, where highly-digital and modularized circuits are desirable.
Figure 1.(Color online) Synthesis-friendly analog circuits design flow.
One direction is to design analog circuits using only logic gates. This way, they directly fit the existing digital synthesis flow. Stochastic flash analog-to-digital converter (ADC) pioneered this direction[
Researchers also explored to build analog standard cells to assist AMS circuit synthesis. In Ref. [5], a synthesized multi-stage noise-shaping (MASH) sigma–delta (ΣΔ) modulator is reported. It is made possible by creating an analog library, including opamp, comparator, transmission gate, and unit capacitor. Each analog cell, including a custom-optimized layout, is treated as a digital standard cell by the APR engine. A synthesized current-steering DAC, is demonstrated in Ref. [6], where the current cells are individually designed and then APRed. These works demonstrate remarkable Verilog-to digital-gate based analog cells are developed to reduce manual efforts for each design. A synthesizable biquad filter reported in Ref. [7] achieves state-of-the-art linearity, where the amplifier is implemented by NAND, NOR, and INV logic gates. High programmability is provided over the gain, bandwidth, and input-referred noise to provide reconfigurability. Still, the usage of this specially designed analog cell is limited to specific architectures – layout synthesis capability. However, they still rely on the pre-optimized analog cells, which have to be developed separately for each specific design or technology node. Hence, they are difficult to generalize to other design specs or circuit types.
Digital-gate based analog cells are developed to reduce manual efforts for each design. A synthesizable biquad filter reported in Ref. [7] achieves state-of-the-art linearity, where the amplifier is implemented by NAND, NOR, and INV logic gates. High programmability is provided over the gain, bandwidth, and input-referred noise to provide reconfigurability. Still, the usage of this specially designed analog cell is limited to specific architectures.
SAR architecture draws attention in recent synthesizable ADC developments owing to the highly-digital nature. A highly automated SAR ADC design is demonstrated in Ref. [8]. Nevertheless, a dedicated custom-made capacitor DAC layout tool is required on top of the standard digital EDA tool. There is still a performance gap between the synthesized SAR ADC and the manually optimized one.
While the conventional voltage-domain analog circuit is challenged by the sub-par analog accuracy in standard cells and APR, time-domain analog signal processing shows promising synthesis friendliness. By representing signals using time-related variables, such as frequency and delay, it allows the circuit to be mostly digital by nature. As a result, time-domain AMS circuits are inherently suitable for synthesis.
A domino-logic ADC is reported in Ref. [9], where the input voltage controls a domino cell chain's delay. The input is quantized by counting the number of cells that the trigger signal propagates through. The highly modularized typology allows the fully automated synthesis of this type of ADC. However, the resolution is still limited to 6-bit because of the inherent nonlinearity of the delay chain.
Recent advancements of all-digital phase-locked loops (PLLs) benefit substantially from the digital-friendly nature of time-domain processing. Consequently, synthesized all-digital PLLs have shown performance comparable to state-of-the-arts[
Inspired by the time-domain PLLs, fully synthesized VCO-based continuous-time ΔΣ modulators (CTDSMs) are reported in Refs. [14, 15]. The analog input is converted into phase and frequency. Then, the quantization is performed by XOR gates instead of conventional voltage domain comparators. This architecture provides noise shaping capability and upconverts component mismatches, thus relaxing APR requirements. As a result, solely implemented by foundry digital standard cells and resistors, it demonstrates resolution beyond 11-ENOB with state-of-the-art energy efficiency, while maintaining a high automation level.
FASoc has carried it further[
As a final remark, although researchers have proposed encouraging solutions in the past decade, they still lack general applicability since detailed optimizations are required for each specific topology or performance metric.
2.2. Procedural layout generation
As mentioned in Section 1, procedural layout generation is often used to generate modules[
Figure 2.(Color online) Procedural analog circuits layout design flow.
Procedural layout generators date back to as early as the works of ILAC[
Recent works on procedural layout generators have also demonstrated the capability of producing results verified by tape-out measurements. Wulff and Ytterdal[
Figure 3.(Color online) An example of the Python script and generated layout of BAG2[
However, procedural layout generators still have a significant amount of manual labor involved in developing parametric cells and incorporating scripts to codify device placement and routing. Nevertheless, these approaches have demonstrated a significant reduction in manual labor in design migration to different technologies. There have also been several works in reducing the amount of manual overhead of procedural generators in layout migration[
2.3. Optimization-based layout synthesis
Another popular paradigm is to cast the layout generation into optimization problems. A typical flow for optimization-based layout synthesis, as shown in Fig. 4, formulates layout considerations as parameters or constraints defined by users. The layout synthesis is through an optimization engine without manual intervention. The high-quality layout is achieved by optimizing specific objectives, such as wirelength and area, under a set of constraints, such as symmetry between devices and design rules. This methodology is similar to digital EDA tools and often borrow ideas from them. It is top-down automation because the layout expert knowledge is applied in formulating the constraints and objectives[
Figure 4.(Color online) Optimization-based layout design flow.
Like digital EDA tools, optimization-based analog layout generation often separates the process into several stages for divide-and-conquer. A common practice is to have three stages, module generation, placement, and routing. The module generator generates the layout of building blocks in a parameterized manner. The placement stage then places the layout from the module generator. In the end, the routing stage connects the nets through metal wires and VIAs.
Module generator is an essential component in optimization-based flow as it provides the layouts of fundamental building blocks, e.g., transistors and resistors. Modern industry custom layout tools, such as Cadence Virtuoso, provide a parameterized device generator (PCells) to produce primary devices' layout. In academia, several frameworks are using customized device generators, such as ALIGN[
Placement takes the basic building block layouts as input and places them on the layout. Unlike the digital placement problem, the scale of AMS placement is often much smaller in the number of modules and more stringent requirements limited by layout-sensitive performance. A pivotal question to AMS placement problem formulation is how to correlate the placement optimization objectives with the layout quality. A well-adopted approach is to formulate the placement problem into a constrained optimization problem. Constraints are imposed to restrict the automated placement to established manual layout design patterns, and objectives encourage the solutions with a smaller area, shorter wirelength, etc. The most-widely-used type of such geometric constraint is the symmetry constraint. Symmetry constraint restricts the pairs of modules to be placed along with one or several symmetric axes. This formulation is mimicking similar techniques in manual layout designs. Symmetry constraint has been widely used in Refs. [1, 40–70]. Similarly, common-centroid is adopted in analog placement problem[
Figure 5.(Color online) Examples of placement constraints. (a) Symmetry constraint. (b) Common-centroid constraint.
A recent trend in literature for analog placement is to explore methods for performance-driven optimization. In the work[
Routing takes the placed layout and connects the nets with metal wires and VIAs. Analog routing usually is similar to digital routing with additional considerations on symmetry constraints[
Recently, there are rising interests in fully automated or “no-human-in-the-loop” physical design flow[
Figure 6.The overall flow of MAGICAL[
In the existing optimization-based AMS layout automation framework, several challenges are remaining unresolved. First, there yet lacks a principal method in formulating the optimization problems. The existing geometric constraints are distilled from manual layout heuristics, which are design-dependent and technology-dependent[
3. Recent research trends
In this section, we introduce several recent efforts and present our view on the research trend in this area.
3.1. Layout performance prediction
A significant challenge in automatic AMS layout synthesis is the lack of an effective method to model the layout effects on circuit performance. Fig. 7 shows a potential flow of performance prediction-assisted automated layout generation flow. A performance modeling can give feedback to automatic layout generation and guide the tool to generate high-performance layouts.
Figure 7.(Color online) Layout generator with layout performance prediction.
The authors of the work[
In Ref. [82], a preliminary attempt to model the circuit performance from layouts is presented. The idea is further extended in the work[
3.2. Leveraging human knowledge from existing layouts
Another trend of applying ML to AMS layout is to leverage ML to learn the manual layout techniques from existing layouts. Fig. 8 shows a potential flow for automatically learning from manual layouts. Using human layouts are golden examples, a machine learning model can learn the strategies in designing layouts (the training phase) and use the learned model for new designs (the inference phase).
Figure 8.(Color online) A flow for learning knowledge from manual layouts.
Generating wells and inverting contacts are often customized-designed in manual layouts. On the other hand, existing AMS layout synthesis frameworks often integrate the well generation in module generation. For example, MAGICAL generates separate NWELL contacts for each PMOS device[
A similar idea is used in analog routing. Current analog routing in optimization-based AMS layout synthesis is usually a constrained optimization problem. Manual layout techniques are imposed as constraints, and analog routers usually optimize for the wirelength and area. However, it raises whether this constraint-driven methodology is suitable for a more extensive range of circuits. GeniusRoute[
Figure 9.GeniusRoute framwork. (a) Training phase. (b) Inference phase[
In both cases, supervised generative learning is automatically used to learn the manual layout techniques from existing designs. To some degree, it relieves the efforts to design heuristics in automatic AMS place and route algorithms and provides a new approach to learn human knowledge from existing layouts.
3.3. Automatic constraint generation
AMS CAD flows rely on designers to provide layout constraints that are honored during layout implementation. These constraints are often design-dependent and related to performance-sensitive layout effects. Common constraint examples are device proximity and dummy insertions during device placement and increased wire spacing for reduced net coupling during routing. The analog circuits' performance is often closely related to these detailed layout implementations, and layout dependant effects could significantly degrade circuit performance and even change circuit functionality. Thus by enforcing these constraints during layout implementation, the designers hope to mitigate parasitic and layout dependent effects on the final post-layout circuit performance.
Symmetry constraints are one of the most essential and widely adopted constraints applied during analog layout synthesis. Analog designs frequently use differential topologies to reject common-mode noise and enhance circuit robustness. Mismatch in the devices of these topologies would significantly degrade the circuit performance. In layout designs, these devices need to be placed and routed symmetrically to enforce matching. Although most layout heuristic constraints are design-dependent, several attempts to automatically extract symmetry constraints from the design netlist.
Existing works for symmetry constraint detection can be categorized into two major types: 1) circuit analysis and 2) graph matching. Charbon et al.[
Recent works have improved prior approaches and scaling to larger system-level designs. Liu et al.[
3.4. AMS CAD with in-loop-simulation
Incorporating simulation in AMS CAD is not a new idea. In early work[
Figure 10.A flow with in-loop simulation.
The work[
The recent development of AMS layout synthesis frameworks, such as ALIGN, BAG, and MAGICAL, provides the essential to integrate layout knowledge to research problems.
4. Open questions in analog layout automation
Amid recent fast development of automatic AMS layout synthesis, several open questions and challenges are yet to be solved. This section presents our view on future directions on research in automating AMS layout design.
4.1. Open-source efforts on comprehensive layout synthesis flow
It takes considerable efforts to compose a complete layout synthesis flow from fundamental devices to detailed routing[
However, the open-source environment is not yet mature. For BAG, layout design needs manual efforts, and the open-source layout design templates are relatively limited in number. On the other hand, both ALIGN and MAGICAL have supported selected technologies in the current public version. A major challenge is on the development overhead of transferring tools to other technologies. For example, the design rule and device layouts are different in different technologies.
An active open-source community also enables collaborations among different projects. In the current open-source AMS layout generator tools, some efforts are repetitive and overlapping with each other. For example, all of the ALIGN, BAG, and MAGICAL have implemented the device generators. A possible approach is to standardize the interface and file formats between the tools. For example, similar to digital, physical design flow, the open-source AMS layout synthesis tools can use standardized exchangeable file formats to enable the integrated usage of different tools. We believe it is the future trend of the open-source community for AMS layout synthesis.
4.2. Sign-off-quality layout generation
For optimization-based approaches, an open question is on how to obtain sign-off quality layouts. In other words, how to fill in the current gap between optimization to real circuit performance.
A potential direction is to use the ML method to model the layout effects on circuit performance. Preliminary research is surveyed in Section 3.1. However, this work has not answered the question of how to optimize the performance directly. Even with accurate performance modeling, the optimization method to consider the ML model is remaining unanswered.
Another direction is to integrate more in-loop simulations. As introduced in Section 3.4, post-layout simulations have already been successfully used in automatic layout generation of analog building blocks. However, due to the unacceptable simulation time costs, this approach is difficult to be applied to larger system-level designs. Further research in this direction might answer the open question of ensuring the layout quality from automatic tools.
On the other hand, with both the advances in placement and routing algorithm, optimization-based tools have demonstrated the capability to generate layouts for mixed-signal ADCs with tape-out-ready quality[
4.3. Understanding the designs
AMS designs differ in functionalities. Furthermore, understanding the circuit design is crucial in fully automatic layout generation. For example, an operational amplifier and a comparator may have different ideal layout strategies for different considerations. Furthermore, extracting suitable constraints in optimization-based analog place and route from schematic also needs knowledge from circuit design. Currently, state-of-the-art constraint generations are focusing on symmetry[
5. Conclusion
This paper presents an overview of the current frameworks of automatic layout generation for analog and mixed-signal circuits. Recent advances and trends in state-of-the-art research are summarized. We review the significant challenges of AMS layout generation and survey the latest advancements in open-source frameworks with ML that addresses those open questions.
Acknowledgements
This work is supported in part by the NSF under Grant No. 1704758, and the DARPA IDEA program.
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