• Microelectronics
  • Vol. 52, Issue 2, 253 (2022)
LI Rui1, TANG He1, WU Jin2, GUO Xuan2, ZHOU Lei2, JI Eryou2, and PENG Xizhu1
Author Affiliations
  • 1[in Chinese]
  • 2[in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.zjea022 Cite this Article
    LI Rui, TANG He, WU Jin, GUO Xuan, ZHOU Lei, JI Eryou, PENG Xizhu. A TI ADC Timing Mismatch Calibration Algorithm Based on Delay Filtering[J]. Microelectronics, 2022, 52(2): 253 Copy Citation Text show less
    References

    [1] LI J, WU S Y, LIU Y, et al. A digital timing mismatch calibration technique in time-interleaved ADCs [J]. IEEE Trans Circ & Syst II: Expr Bri, 2014, 61(7): 486-490.

    [2] BLACK W C, HODGES D A. Time interleaved converter arrays [J]. IEEE J Sol Sta Circ, 1980, 15(6): 1022-1029.

    [3] VOGEL C. Comprehensive, error analysis of combined channel mismatch effects in time-interleaved ADCs [C]// Proceed 20th IEEE Instrum Technol Conf. 2003: 733-738.

    [4] EL-CHAMMAS M, MURMANN B. General analysis on the impact of phase-skew in time-interleaved ADCs [J]. IEEE Trans Circ & Syst I: Regu Pap, 2009, 56(5): 902-910.

    [5] JENQ Y C. Digital spectra of nonuniformly sampled signals: fundamentals and high-speed waveform digitizers [J]. IEEE Trans Instrum & Measur, 1988, 37(2): 245-251.

    [6] KUROSAWA N, KOBAYASHI H, MARUYAMA K, et al. Explicit analysis of channel mismatch effects in time-interleaved ADC systems [J]. IEEE Trans Circ & Syst I: Fundam Theo & Appl, 2001, 48(3): 261-271.

    [7] JIA H B, GUO X, WU D Y, et al. A 12-bit 24 GS/s four-channel pipelined ADC with a novel on-chip timing mismatch calibration [J]. Elec, 2020, 9(6): 910.

    [8] WEI H G, ZHANG P, SAHOO B D, et al. An 8 bit 4 Gs/s 120 mW CMOS ADC [J]. IEEE J Sol Sta Circ, 2014, 49(8): 1751-1761.

    LI Rui, TANG He, WU Jin, GUO Xuan, ZHOU Lei, JI Eryou, PENG Xizhu. A TI ADC Timing Mismatch Calibration Algorithm Based on Delay Filtering[J]. Microelectronics, 2022, 52(2): 253
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