• Microelectronics
  • Vol. 52, Issue 5, 915 (2022)
WANG Jun
Author Affiliations
  • [in Chinese]
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    DOI: 10.13911/j.cnki.1004-3365.220153 Cite this Article
    WANG Jun. Study on ESD Protection Performance of Gated Diode in 14 nm FinFET Process[J]. Microelectronics, 2022, 52(5): 915 Copy Citation Text show less

    Abstract

    Diode is still widely used in I/O ESD application when the process advances to FinFET technology, though the robustness per unit width of the diode is lower than planar process. This paper detailed ESD performance parameters based on 14 nm FinFET process, such as failure current (It2), failure voltage (Vt2), failure current per unit width (It2/Width) and failure current per unit area (It2/Area) of Gated diode. The tendencies of ESD device characteristics with dimension parameters were given. It is found that the It2/Width decreases while the It2/Area increases with the increase of number of fins (nfin), the multiplication factor along the fin (Fn) and the multiplication factor across the fin (Yarray). The on-resistance is almost not affected by nfin and Fn.