A high-speed, low-power-consumption L-band charge-pump phase-locked loop (CPPLL) with multi-input frequency selection and multilevel output frequency modulation range was designed in SMIC 180 nm/1.8 V CMOS technology. A 4-to-1 data selector was added at the input end to realize tracking and phase-locking of signal at multi-frequency point. At the output end, a programmable dual-modulus prescaler based on a novel P/S type counter was designed to realize high-precision frequency division and programmable continuous bit output. The experimental results show that, the locking time from startup to stabled 1.1 GHz output is 1.5 μs and the power consumption can be lowered to 1.2 mW. In addition, the 2~15 bits continuous programmable frequency division can be realized with frequency tuning range of 73 MHz to 500 MHz. Finally, the layout design of the overall PLL circuit is implemented and the area is only 0.027 mm2, which had been transferred to SMIC for chip tapeout. The proposed L-band PLL can be effectively employed in wireless communication and RF signal processing systems, such as satellite down-frequency-receiving, optical signal modulation and digital audio broadcasting (T-DAB).