[1] PATYUCHENKO A. High performance data converters for medical imaging systems ［EB/OL］. https://www. analog.com/en/analog-dialogue/articles/high-performance-data-converters-for-medical-imaging-systems.html, 2019.

[2] HARPE P. Successive approximation analog-to-digital converters: improving power efficiency and conversion speed ［J］. IEEE Sol Sta Circ Magaz, 2016, 8(4): 64-73.

[3] WANG J C, HUNG T C, KUO T H. A calibration-free 14-b 07-mW 100-MS/s pipelined-SAR ADC using a weighted-averaging correlated level shifting technique ［J］. IEEE J Sol Sta Circ, 2020, 55(12): 3271-3280.

[4] YU Q, ZHOU X, HU K, et al. A 908 ENOB 10 b 400 MS/s subranging SAR ADC with subsetted CDAC and PDAS in 40 nm CMOS ［C］// IEEE 47th ESSCC. Grenoble, France. 2021: 391-394.

[7] HUMMERSTON D, HURRELL P. An 18-bit 2 MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with -107 dB THD at 100 kHz ［C］// IEEE Symp VLSI Circ. Kyoto, Japan. 2017: 280-281.

[8] CHEN H, ZHOU X, YU Q, et al. A >3 GHz ERBW 11 GS/s 8 b two-step SAR ADC with recursive-weight DAC ［C］// IEEE Symp VLSI Circ. Honolulu, HI, USA. 2018: 97-98.

[9] LIU C C, CHANG S J, HUANG G Y, et al. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure ［J］. IEEE J Sol Sta Circ, 2010, 45(4): 731-740.

[10] KIM J E, YOO T, BAEK K H, et al. A balanced sampling switch for high linearity and a wide temperature range in low power SAR ADCs ［J］. Elec Lett, 2019, 55(24): 1273-1275.

[11] IIZUKA T, ITO T, ABIDI A A. Comprehensive analysis of distortion in the passive FET sample-and-hold circuit ［J］. IEEE Trans Circ Syst I: Regu Pap, 2018, 65(4): 1157-1173.

[12] LI Y, ZHOU Y, CHIU Y. A compact calibration model for linearizing CMOS sample-and-hold circuits ［J］. IEEE Trans Circ Syst II: Expr Bri, 2020, 67(1): 2327-2331.