• Infrared Technology
  • Vol. 42, Issue 11, 1022 (2020)
[in Chinese]*, [in Chinese], and [in Chinese]
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  • [in Chinese]
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    DOI: Cite this Article
    [in Chinese], [in Chinese], [in Chinese]. Verification Protocol for Improving Communication Stability Between FPGAs[J]. Infrared Technology, 2020, 42(11): 1022 Copy Citation Text show less
    References

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    [2] HOU Q L, XU K J, FANG M, et al. A DSP-based signal processing methd and system for CMF[J]. Measurement Journal of the International Measurement Confederation, 2013, 46(7): 2184-2192.

    [5] Alkafi A, Imran R, Islam M. Development of FSM based Running Disparity Controlled 8b/10b Encoder/Decoder with Fast Error Detection Mechanism[J]. HCTL Open IJTIR, 2013(2): 2321-1814.

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    [9] WONG A C, Borrelli C J, Jones L, et al. Transceiver for providing a clock signal[P]. [2013-8-8]. U.S. Patent 13,962,468.

    [11] Xilinx. 7 Series FPGAs GTX/GTH Transceivers User Guide [Z]. America: Xilinx Inc, 2018.

    [12] Wirthlin MJ, Takai H. Harding. A soft error rate estimations of the Kintex-7 FPGA within the ATLAS Liquid Argon (LAr) Calorimeter [J]. Journal of Instrumentation, 2014, 9(1): 1-8.

    [13] Herrera-Alzu I,Lopez-Vallejo M. Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers[J]. IEEE Transac-tions on Nuclear Science, 2013, 60(1): 376-385.

    [14] Xilinx. Vivado Design Suite 7 Series FPGA and Zynq-7000 All Programmable SoC Libraries Guide [Z]. America: Xilinx Inc, 2017.

    [in Chinese], [in Chinese], [in Chinese]. Verification Protocol for Improving Communication Stability Between FPGAs[J]. Infrared Technology, 2020, 42(11): 1022
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